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TL16C552FNRG4 Datasheet(PDF) 4 Page - Texas Instruments
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TL16C552FNRG4 Datasheet(HTML) 4 Page - Texas Instruments
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DUAL ASYCHRONOUS COMMUNICATIONS ELEMENT
SLLS102B − DECEMBER 1990 − REVISED MARCH 1996
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251−1443
Terminal Functions (continued)
Serial channel interrupts. INT0 and INT1 are 3-state serial channel interrupt outputs (enabled by bit
3 of the MCR) that go active (high) when one of the following interrupts has an active (high) condition
and is enabled by the interrupt enable register of its associated channel: receiver error flag, received
data available, transmitter holding register empty, and modem status. The interrupt is cleared upon
appropriate service. When reset, the interrupt output is in the high-impedance state.
Printer port interrupt. INT2 is an active-high, 3-state output generated by the positive transition of ACK.
It is enabled by bit 4 of the write control register. Upon a reset, the interrupt output is in the
high-impedance state. Its mode is also controlled by ENIRQ.
PD0 − PD7
53 − 46
Parallel data bits (0 − 7). These eight lines (PD0 − PD7) provide a byte wide input or output port to the
Printer paper empty. PE is an input line from the printer that goes high when the printer runs out of
Printer enhancement mode. When low, PEMD enables the write data register to the PD0 − PD7 lines.
A high on this signal allows direction control of the PD0 − PD7 port by the DIR bit in the control register.
PEMD is usually tied low for the printer operation.
Reset. When low, RESET forces the TL16C552 into an idle mode in which all serial data activities are
suspended. The modem control register along with its associated outputs are cleared. The line status
register is cleared except for the THRE and TEMT bits, which are set. All functions of the device remain
in an idle state until programmed to resume serial data activities. This input has a hysteresis level of
typically 400 mV.
Request to send outputs. RTSx is asserted low by setting MCR1, bit 1 of its UARTs modem control
register. Both RTSx terminals are set by RESET. A low on the RTSx terminal indicates that its ACE has
data ready to transmit. In half-duplex operations, RTSx controls the direction of the line.
Receiver ready. RXRDY0 and RXRDY1 are receiver direct memory access (DMA) signaling
terminals. One of two types of DMA signaling can be selected using FIFO control register bit 3 (FCR3)
when operating in the FIFO mode. Only DMA mode 0 is allowed when operating in the TL16C450
mode. For signal transfer DMA (a transfer is made between CPU bus cycles), mode 0 is used. Multiple
transfers that are made continuously until the receiver FIFO has been emptied are supported by
Mode 0. RXRDYx is active (low) when in the FIFO mode (FCR0=1, FCR3=0) or when in the TL16C450
mode (FCR0=0) and the receiver FIFO or receiver holding register contain at least one character.
When there are no more characters in the receiver FIFO or receiver holding register, the RXRDYx
terminal goes inactive (high).
Mode 1. RXRDYx goes active (low) in the FIFO mode (FCR0=1) when FCR3=1 and the time-out or
trigger levels have been reached. It goes inactive (high) when the FIFO or receiver holding register is
Ring indicator inputs. RI0 and RI1 are modem control inputs. Their condition is tested by reading
MSR6 (RI) of each ACE. The modem status register outputs trailing edge of ring indicator (TERI or
MSR2) that indicates whether either input has changed states from high to low since the previous
reading of the modem status register.
Serial data inputs. SIN0 and SIN1 are serial data inputs that move information from the communication
line or modem to the TL16C552 receiver circuits. Mark (set) is a high state and a space (cleared) is
low state. Data on the serial data inputs is disabled when operating in the loop mode.
Printer selected. SLCT is an input line from the printer that goes high when the printer has been
Line printer select. SLIN is an open-drain input that selects the printer when it is active (low). This
terminal has an internal pullup resistor to VDD of approximately 10 kΩ.
Serial data outputs. SOUT0 and SOUT1 are the serial data outputs from the ACE transmitter circuitry.
A mark is a high state and a space is a low state. Each SOUT is held in the mark condition when the
transmitter is disabled, when RESET is true (low), when the transmitter register is empty, or when in
the loop mode.
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