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TL16C552FNRG4 Datasheet(PDF) 31 Page - Texas Instruments

Part No. TL16C552FNRG4
Description  DUAL ASYCHRONOUS COMMUNICATIONS ELEMENT
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Maker  TI1 [Texas Instruments]
Homepage  http://www.ti.com
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TL16C552FNRG4 Datasheet(HTML) 31 Page - Texas Instruments

 
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TL16C552
DUAL ASYCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS102B − DECEMBER 1990 − REVISED MARCH 1996
31
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251−1443
PRINCIPLES OF OPERATION
programmable baud generator (continued)
Table 16. Baud Rates Using a 8.192-MHz Crystal
BAUD RATE
DESIRED
DIVISOR (N) USED TO
GENERATE 16 X CLOCK
PERCENT ERROR DIFFERENCE
BETWEEN DESIRED AND ACTUAL
50
75
110
134.5
150
300
600
1200
1800
2000
2400
3600
4800
7200
9600
19200
38400
56000
128000
256000
512000
1000
6667
4545
3717
3333
1667
833
417
277
250
208
139
104
69
52
26
13
9
4
2
1
0.005
0.010
0.013
0.010
0.020
0.040
0.080
0.080
0.160
0.080
0.160
0.644
0.160
0.160
0.160
0.790
2.344
2.344
2.400
programming
The serial channel of the ACE is programmed by the control registers: LCR, IER, DLL, DLM, MCR, and FCR.
These control words define the character length, number of stop bits, parity, baud rate, and modem interface.
While the control registers can be written in any order, the IER should be written last because it controls the
interrupt enables. Once the serial channel is programmed and operational, these registers can be updated any
time the ACE serial channel is not transmitting or receiving data.
receiver
Serial asynchronous data is input into the SIN terminal. The ACE continually searches for a high-to-low
transition
from the idle state. When the transition is detected, a counter is cleared, and counts the 16
× clock to 7 1/2, which
is the center of the start bit. The start bit is valid when the SIN is still low. Verifying the start bits prevents the
receiver from assembling a false data character due to a low-going noise spike on the SIN input.
The LCR determines the number of data bits in a character [LCR0, LCR1]. When parity is used LCR3 and the
polarity of parity LCR4 are needed. Status for the receiver is provided in the LSR. When a full character is
received, including parity and stop bits, the data received indication in LSR0 is set. The CPU reads the RBR,
which clears LSR0. If the character is not read prior to a new character transfer from the RSR to the RBR, the
OE status indication is set in LSR1. When there is a PE, the PE bit is set in LSR2. If a stop bit is not detected,
a FE indication is set in LSR3.
When the data into SIN is a symmetrical square wave, the center of the data cells occurs within
±3.125% of the
actual center, providing an error margin of 46.875%. The start bit can begin as much as one 16
× clock cycle
prior to being detected.


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