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TL16C552FNRG4 Datasheet(PDF) 3 Page - Texas Instruments
TI1 [Texas Instruments]
TL16C552FNRG4 Datasheet(HTML) 3 Page - Texas Instruments
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DUAL ASYCHRONOUS COMMUNICATIONS ELEMENT
SLLS102B − DECEMBER 1990 − REVISED MARCH 1996
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251−1443
Line printer acknowledge. ACK goes low to indicate a successful data transfer has taken place.
It generates a printer port interrupt during its positive transition.
Line printer autofeed. AFD is an open-drain line that provides the printer with an active-low signal
when continuous form paper is to be autofed to the printer. This terminal has an internal pullup
resistor to VDD of approximately 10 kΩ.
A0, A1, A2
35, 34, 33
Address lines A0 − A2. A0, A1, and A2 select the internal registers during CPU bus operations. See
Table 2 for the decode of the serial channels and Table 13 for the decode of the parallel printer port.
Bus buffer output. BDO is an active-high output that is asserted when either serial channel or the
parallel port is read. This output can control the system bus driver (74LS245).
Line printer busy. BUSY is an input line from the printer that goes high when the printer is not ready
to accept data.
Clock input. CLK is an external clock input to the baud rate divisor of each ACE.
CS0, CS1, CS2
32, 3, 38
Chip selects. CS0, CS1, and CS2 act as an enable for the write and read signals for the serial
channels 1 (CS0) and 2 (CS1). CS2 enables the signals to the printer port.
Clear to send inputs. The logical state of CTS0 or CTS1 is reflected in the CTS bit of the modem
status register (CTS is bit 4 of the modem status register, written MSR4) of each ACE. A change
of state in either CTS terminal, since the previous reading of the associated modem status register,
causes the setting of delta clear to send (
∆CTS) bit (MSR0) of each modem status register.
DB0 − DB7
14 − 21
Data bits DB0 − DB7. The data bus provides eight 3-state I/O lines for the transfer of data, control,
and status information between the TL16C552 and the CPU. These lines are normally in a
high-impedance state except during read operations. D0 is the least significant bit (LSB) and is the
first serial data bit to be received or transmitted.
Data carrier detect. DCD is a modem input. Its condition can be tested by the CPU by reading the
MSR7 (DCD) bit of the modem status registers. The MSR3 (delta data carrier detect or
of the modem status register indicates whether the DCD input has changed states since the
previous reading of the modem status register. DCD has no affect on the receiver.
Data set ready inputs. The logical state of DSR0 and DSR1 is reflected in MSR5 of its associated
modem status register. The MSR1 (delta data set ready or
∆DSR) bit indicates whether the
associated DSR terminal has changed states since the previous reading of the modem status
Data terminal ready lines. DTR0 and DTR1 can be asserted low by setting modem control register
bit 0 (MCR0) of its associated ACE. This signal is asserted high by clearing the DTR bit (MCR0)
or whenever a reset occurs. When active (low), the DTR terminal indicates that its ACE is ready
to receive data.
Parallel port interrupt source mode selection. When ENIRQ is low, the PC/AT mode of interrupts
is enabled. In this mode, the INT2 output is internally connected to the ACK input. When the ENIRQ
input is tied high, the INT2 output is internally tied to the PRINT signal in the line printer status
register. INT2 is latched high on rising edge of ACK.
Line printer error. ERR is an input line from the printer. The printer reports an error by holding this
line low during the error condition.
7, 27, 54
Ground (0 V). All terminals must be tied to ground for proper operation.
Line printer initialize. INIT is an open-drain line that provides the printer with an active-low signal,
which allows the printer initialization routine to be started. This terminal has an internal pullup
resistor to VDD of approximately 10 kΩ.
Input/output read strobe. IOR is an active-low input that enables the selected channel to output
data to the data bus (DB0 − DB7). The data output depends upon the register selected by the
address inputs A0, A1, A2, and chip select. Chip select 0 (CS0) selects ACE #1, chip select 1 (CS1)
selects ACE #2, and chip select 2 (CS2) selects the printer port.
Input/output write strobe. IOW is an active-low input causing data from the data bus to be input to
either ACE or to the parallel port. The destination depends upon the register selected by the address
inputs A0, A1, A2, and chip selects CS0, CS1, and CS2.
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