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TL16C552FNRG4 Datasheet(PDF) 28 Page - Texas Instruments

Part No. TL16C552FNRG4
Description  DUAL ASYCHRONOUS COMMUNICATIONS ELEMENT
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Maker  TI1 [Texas Instruments]
Homepage  http://www.ti.com
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TL16C552FNRG4 Datasheet(HTML) 28 Page - Texas Instruments

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TL16C552
DUAL ASYCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS102B − DECEMBER 1990 − REVISED MARCH 1996
28
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251−1443
PRINCIPLES OF OPERATION
modem status register (MSR)
The MSR provides the CPU with status of the modem input lines from the modem or peripheral devices. The
MSR allows the CPU to read the serial channel modem signal inputs by accessing the data bus interface of the
ACE in addition to the current status of four bits of the MSR that indicate whether the modem inputs have
changed since the last reading of the MSR. The delta status bits are set when a control input from the modem
changes state and cleared when the CPU reads the MSR.
The modem input lines are CTS, DSR, RI, and DCD. MSR4 − MSR7 are status indications of these lines. A
status bit = 1 indicates the input is a low. A status bit = 0 indicates the input is high. When the modem status
interrupt in the interrupt enable register is enabled (IER3), an interrupt is generated whenever MSR0 − MSR3
is set. The MSR is a priority 4 interrupt. The contents of the MSR are described in Table 11.
Table 11. Modem Status Register Bits
MSR BIT
MNEMONIC
DESCRIPTION
MSR0
∆CTS
Delta clear to send
MSR1
∆DSR
Delta data set ready
MSR2
TERI
Trailing edge of ring indicator
MSR3
∆DCD
Delta data carrier detect
MSR4
CTS
Clear to send
MSR5
DSR
Data set ready
MSR6
RI
Ring indicator
MSR7
DCD
Data carrier detect
D Bit 0: MSR0 is the delta clear to send (∆CTS) bit. ∆CTS displays that the CTS input to the serial channel
has changed state since it was last read by the CPU.
D Bit 1: MSR1 is the delta data set ready (∆DSR) bit. ∆DSR indicates that the DSR input to the serial channel
has changed state since the last time it was read by the CPU.
D Bit 2: MSR2 is the trailing edge of ring indicator (TERI) bit. TERI indicates that the RI input to the serial
channel has changed states from low to high since the last time it was read by the CPU. High-to-low
transitions on RI do not activate TERI.
D Bit 3: MSR3 is the delta data carrier detect (∆DCD) bit. ∆DCD indicates that the DCD input to the serial
channel has changed state since the last time it was read by the CPU.
D Bit 4: MSR4 is the clear to send (CTS) bit. CTS is the complement of the CTS input from the modem
indicating to the serial channel that the modem is ready to receive data from SOUT. When the serial channel
is in the loop mode ((MCR4 = 1), MSR4 reflects the value of RTS in the MCR.
D Bit 5: MSR5 is the data set ready (DSR) bit. DSR is the complement of the DSR input from the modem to
the serial channel that indicates that the modem is ready to provide received data to the serial channel
receiver circuitry. When the channel is in the loop mode (MCR4=1), MSR5 reflects the value of DTR in the
MCR.
D Bit 6: MSR6 is the ring indicator (RI) bit. RI is the complement of the RI input. When the channel is in the
loop mode (MCR4=1), MSR6 reflects the value of OUT1 in the MCR.
D Bit 7: MSR7 is the data carrier detect (DCD) bit. DCD indicates the status of the data carrier detect (DCD)
input. When the channel is in the loop mode (MCR4=1), MSR7 reflects the value of OUT2 in the MCR.


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