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TL16C552FNRG4 Datasheet(PDF) 25 Page - Texas Instruments

Part No. TL16C552FNRG4
Description  DUAL ASYCHRONOUS COMMUNICATIONS ELEMENT
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Maker  TI1 [Texas Instruments]
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TL16C552FNRG4 Datasheet(HTML) 25 Page - Texas Instruments

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TL16C552
DUAL ASYCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS102B − DECEMBER 1990 − REVISED MARCH 1996
25
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251−1443
PRINCIPLES OF OPERATION
line status register (LSR) (continued)
D Bit 0: LSR0 is the data ready (DR) bit. DR is set high when an incoming character has been received and
transferred into the receiver buffer register or the FIFO. LSR0 is cleared by a CPU read of the data in the
receiver buffer register or the FIFO.
D Bit 1: SR1 is the overrun error (OE) bit. OE indicates that data in the receiver buffer register was not read
by the CPU before the next character was transferred into the receiver buffer register overwriting the
previous character. The OE indicator is cleared whenever the CPU reads the contents of the LSR. An OE
occurs in the FIFO mode after the FIFO is full and the next character is completely received. The OE is
detected by the CPU on the first LSR read after the overrun happens. The character in the shift register is
not transferred to the FIFO but it is overwritten.
D Bit 2: LSR2 is the parity error (PE) bit. PE indicates that the received data character does not have the
correct parity as selected by LCR3 and LCR4. The PE bit is set upon detection of a parity error and is cleared
when the CPU reads the contents of the LSR. In the FIFO mode, the parity error is associated with a
particular character in the FIFO. LSR2 reflects the error when the character is at the top of the FIFO.
D Bit 3: LSR3 is the framing error (FE) bit. FE indicates that the received character did not have a valid stop
bit. LSR3 is set when the stop bit following the last data bit or parity bit is detected as a zero bit (spacing
level). The FE indicator is cleared when the CPU reads the contents of the LSR. In the FIFO mode, the
framing error is associated with a particular character in the FIFO. LSR3 reflects the error when the
character is at the top of the FIFO.
D Bit 4: LSR4 is the break interrupt (BI) bit. BI is set when the received data input is held in the spacing
(cleared) state for longer than a full word transmission time (start bit + data bits + parity + stop bits). The
BI indicator is cleared when the CPU reads the contents of the LSR. In the FIFO mode, this is associated
with a particular character in the FIFO. LSR2 reflects the BI when the break character is at the top of the
FIFO. The error is detected by the CPU when its associated character is at the top of the FIFO during the
first LSR read. Only one zero character is loaded into the FIFO when BI occurs.
LSR1 − LSR4 are the error conditions that produce a receiver line status interrupt (priority 1 interrupt in the
interrupt identification register) when any of the conditions are detected. This interrupt is enabled by setting
IER2=1 in the interrupt enable register.
D Bit 5: LSR5 is the THRE bit. THRE indicates that the ACE is ready to accept a new character for
transmission. The THRE bit is set when a character is transferred from the transmitter holding register
(THR) into the transmitter shift register (TSR). LSR5 is cleared by the loading of the transmitter holding
register by the CPU. LSR5 is not reset by a CPU read of the LSR. In the FIFO mode when the transmitter
FIFO is empty, this bit is set. It is cleared when one byte is written to the transmitter FIFO. When the THRE
interrupt is enabled by IER1, THRE causes a priority 3 interrupt in the IIR. When THRE is the interrupt source
indicated in IIR, INTRPT is cleared by a read of the IIR.
D Bit 6: LSR6 is the transmitter empty (TEMT) bit. TEMT is set when the THR and the TSR are both empty.
LSR6 is cleared when a character is loaded into the THR and remains low until the character is transferred
out of SOUT. TEMT is not cleared by a CPU read of the LSR. In the FIFO mode, when both the transmitter
FIFO and shift register are empty, this bit is set.
D Bit 7: LSR7 is the receiver FIFO error bit. The LSR7 bit is always cleared in the TL16C450 mode. In FIFO
mode, it is set when at least one of the following data errors is in the FIFO: PE, FE, or BI indication. It is
cleared when the CPU reads the LSR if there are no subsequent errors in the FIFO.


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