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TL16C552FNRG4 Datasheet(PDF) 19 Page - Texas Instruments
TI1 [Texas Instruments]
TL16C552FNRG4 Datasheet(HTML) 19 Page - Texas Instruments
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DUAL ASYCHRONOUS COMMUNICATIONS ELEMENT
SLLS102B − DECEMBER 1990 − REVISED MARCH 1996
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251−1443
PRINCIPLES OF OPERATION
FIFO interrupt mode operation (continued)
A FIFO timeout interrupt occurs when the following conditions exist:
Minimum of one character in FIFO
Last received serial character was longer than four continuous previous character times ago (if two stop
bits are programmed, the second one is included in the time delay).
The last CPU read of the FIFO was more than four continuous character times earlier. At 300 baud and
12-bit characters, the FIFO time-out interrupt causes a latency of 160 ms maximum from received
character to interrupt issued.
By using the RCLK input for a clock signal, the character times can be calculated. (The delay is proportional
to the baud rate.)
The time-out timer is reset after the CPU reads the receiver FIFO or after a new character is received, when
there has been no time-out interrupt.
A time-out interrupt is cleared and the timer is reset when the CPU reads a character from the receiver FIFO.
Transmitter interrupts occur as follows when the transmitter and transmitter FIFO interrupts are enabled
(FCRO = 1, IER = 1).
When the transmitter FIFO is empty, the THR interrupt (IIR = 02) occurs. The interrupt is cleared as soon
as the THR is written to or the IIR is read. One to sixteen characters can be written to the transmit FIFO when
servicing this interrupt.
The transmitter FIFO empty indications are delayed one character time minus the last stop bit time
whenever the following occurs:
THRE = 1 and there has not been a minimum of two bytes at the same time in transmitter FIFO, since the
last THRE = 1. The first transmitter interrupt after changing FCR0 is immediate, however, assuming it is
Receiver FIFO trigger level and character time-out interrupts have the same priority as the received data
available interrupt. The THRE interrupt has the same priority as the transmitter FIFO empty interrupt.
FIFO polled mode operation
Clearing IER0, IER1, IER2, IER3, or all, with FCR0 = 1, puts the ACE into the FIFO polled mode. Receiver and
transmitter are controlled separately. Therefore, either or both can be in the polled mode.
In the FIFO polled mode, there is no time-out condition indicated or trigger level reached. However, the receiver
and transmitter FIFOs still have the capability of holding characters. The LSR must be read to determine the
interrupt enable register (IER)
The IER independently enables the four serial channel interrupt sources that activate the interrupt (INT0 or
INT1) output. All interrupts are disabled by clearing IER0 − IER3. Interrupts are enabled by setting the
appropriate bits of the IER. Disabling the interrupt system inhibits the IIR and the active (high) interrupt output.
All other system functions operate in their normal manner, including the setting of the LSR and MSR. The
contents of the IER are described in Table 3 and in the following bulleted list.
Bit 0: IER0, when set, enables the received data available interrupt and the time-out interrupts in the FIFO
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