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THS3120IDGN Datasheet(PDF) 2 Page - Texas Instruments |
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THS3120IDGN Datasheet(HTML) 2 Page - Texas Instruments |
2 / 35 page 1 2 3 4 8 7 6 5 NC VIN- VIN+ VS- NC VS+ VOUT NC D,DGN TOP VIEW D,DGN TOP VIEW NC =NoInternalConnection 1 2 3 4 8 7 6 5 REF VIN- VIN+ VS- PD VS+ VOUT NC NC=NoInternalConnection THS3120 THS3121 THS3120 THS3121 SLOS420E – SEPTEMBER 2003 – REVISED OCTOBER 2009........................................................................................................................................ www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. NOTE: The device with the power down option defaults to the ON state if no signal is applied to the PD pin. Additionally, the REF pin functional range is from VS– to (VS+ – 4 V). AVAILABLE OPTIONS(1) PACKAGED DEVICE TA PLASTIC SMALL OUTLINE SOIC (D) PLASTIC MSOP (DGN) (2) (3) SYMBOL THS3120CD THS3120CDGN 0°C to +70°C AQA THS3120CDR THS3120CDGNR THS3120ID THS3120IDGN –40°C to +85°C APN THS3120IDR THS3120IDGNR THS3121CD THS3121CDGN 0°C to +70°C AQO THS3121CDR THS3121CDGNR THS3121ID THS3121IDGN –40°C to +85°C APO THS3121IDR THS3121IDGNR (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. (2) Available in tape and reel. The R suffix standard quantity is 2500 (for example, THS3120CDGNR). (3) The PowerPAD is electrically isolated from all other pins. DISSIPATION RATING TABLE POWER RATING TJ = +125°C PACKAGE θJC (°C/W) θJA (°C/W) TA = +25°C TA = +85°C D-8(1) 38.3 95 1.05 W 421 mW DGN-8(2) 4.7 58.4 1.71 W 685 W (1) These data were taken using the JEDEC standard low-K test PCB. For the JEDEC proposed high-K test PCB, the θJA is +95°C/W with power rating at TA = +25°C of 1.05 W. (2) These data were taken using 2 oz. (56,7 grams) trace and copper pad that is soldered directly to a 3 inch x 3 inch (76,2 mm x 76,2 mm) PCB. For further information, see the Application Information section of this data sheet. 2 Submit Documentation Feedback Copyright © 2003–2009, Texas Instruments Incorporated Product Folder Link(s): THS3120 THS3121 |
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