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THS1401 Datasheet(PDF) 7 Page - Texas Instruments |
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THS1401 Datasheet(HTML) 7 Page - Texas Instruments |
7 / 28 page THS1401 THS1403 THS1408 SLAS248D − DECEMBER 1999 − REVISED SEPTEMBER 2005 www.ti.com 7 PARAMETER MEASUREMENT INFORMATION sample timing The THS1401/3/8 core is based on a pipeline architecture with a latency of 9.5 samples. The conversion results appear on the digital output 9.5 clock cycles after the input signal was sampled. S9 S10 S11 S12 CLK Data Out Analog Input C1 C2 C3 tw(CLK) tw(CLK) td Figure 1. Sample Timing The parallel interface of the THS1401/3/8 ADC features 3-state buffers, making it possible to directly connect it to a data bus. The output buffers are enabled by driving the OE input low. Besides the sample results, it is also possible to read back the values of the control register, the PGA register, and the offset register. Which register is read is determined by the address inputs A[1,0]. The ADC results are available at address 0. The timing of the control signals is described in the following sections. |
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