TFP410-EP

PanelBus

™ DIGITAL TRANSMITTER

SGLS344A − JULY 2006 − REVISED MAY 2011

23

POST OFFICE BOX 655303

The basic access write cycle consists of:

The basic access read cycle consists of:

The start and stop conditions are shown in Figure 10. The high-to-low transition of SDA while SCL is high defines

the start condition. The low-to-high transition of SDA while SCL is high defines the stop condition. Each cycle,

data or address, consists of eight bits of serial data followed by one acknowledge bit generated by the receiving

device. Thus, each data/address cycle contains nine bits (see Figure 11).

SCL

1

2

3

4

5

6

7

8

9

SDA

1

2

3

4

5

6

7

8

9

2

3

4

5

6

7

1

Slave Address

Sub-Address

Data

Stop

89

acknowledge by pulling the SDA line low during the ninth clock cycle if it decodes the address as its address.

During subsequent sub-address and data cycles, the TFP410 responds with acknowledge (see Figure 12). The

sub-address is auto-incremented after each data cycle.

The transmitting device must not drive the SDA signal during the acknowledge cycle so that the receiving device

may drive the SDA signal low. The master indicates a not acknowledge condition (/A) by keeping the SDA signal

high just before it asserts the stop condition (P). This sequence terminates a read cycle (see Figure 13).

The slave address consists of seven bits of address along with one bit of read/write information (read = 1,

write = 0) (see Figure 11 and Figure 12). For the TFP410, the selectable slave addresses (including the R/W

bit) using A[3:1] are 0x70, 0x72, 0x74, 0x76, 0x78, 0x7A, 0x7C, and 0x7E for write cycles, and 0x71, 0x73, 0x75,

0x77, 0x79, 0x7B, 0x7D, and 0x7F for read cycles.