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TDC1000PWR Datasheet(PDF) 35 Page - Texas Instruments |
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TDC1000PWR Datasheet(HTML) 35 Page - Texas Instruments |
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35 / 60 page  TDC1000, TDC1000-Q1 www.ti.com SNAS648B – OCTOBER 2014 – REVISED AUGUST 2015 8.6.1.4 CONFIG_3 Register (address 3h) [reset = 3h] (map) Figure 44. CONFIG_3 Register (MSB) 7 6 5 4 3 2 1 0 (LSB) RESERVED TEMP_MODE TEMP_RTD_SEL TEMP_CLK_DIV BLANKING ECHO_QUAL_THLD R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-3h LEGEND: R/W = Read or write; R = Read only; R/W1C = Read or write 1 to clear Table 8. CONFIG_3 Register Field Descriptions Bit Field Type Reset Description [7] RESERVED R/W 0h 0h: Reserved (default) Temperature measurement channels [6] TEMP_MODE R/W 0h 0h: Measure REF, RTD1 and RTD2 (default) 1h: Measure REF and RTD1 RTD type [5] TEMP_RTD_SEL R/W 0h 0h: PT1000 (default) 1h: PT500 Clock divider for temperature mode [4] TEMP_CLK_DIV R/W 0h 0h: Divide by 8 (default) 1h: Use TX_FREQ_DIV Power blanking in standard TOF measurements. The blanking length is controlled with the TIMING_REG field (see Standard TOF Measurement with Power Blanking). [3] BLANKING R/W 0h 0h: Disable power blanking (default) 1h: Enable power blanking Echo qualification DAC threshold level with respect to VCOM 0h: –35 mV 1h: –50 mV 2h: –75 mV [2:0] ECHO_QUAL_THLD R/W 3h 3h: –125 mV (default) 4h: –220 mV 5h: –410 mV 6h: –775 mV 7h: –1500 mV Copyright © 2014–2015, Texas Instruments Incorporated Submit Documentation Feedback 35 Product Folder Links: TDC1000 TDC1000-Q1 |
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