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IDT7034S15PF Datasheet(PDF) 1 Page - Integrated Device Technology |
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IDT7034S15PF Datasheet(HTML) 1 Page - Integrated Device Technology |
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1 / 19 page  ©1999 Integrated Device Technology, Inc. SEPTEMBER 1999 DSC 4089/6 1 IDT7034S/L HIGH-SPEED 4K x 18 DUAL-PORT STATIC RAM Features: x True Dual-Ported memory cells which allow simultaneous reads of the same memory location x High-speed access Commercial: 15/20ns (max.) x Low-power operation IDT7034S Active: 850mW (typ.) Standby: 5mW (typ.) IDT7034L Active: 850mW (typ.) Standby: 1mW (typ.) x Separate upper-byte and lower-byte control for multiplexed bus compatibility x IDT7034 easily expands data bus width to 36 bits or more using the Master/Slave select when cascading more than one device x M/S = H for BUSY output flag on Master M/S = L for BUSY input on Slave x Interrupt Flag x On-chip port arbitration logic x Full on-chip hardware support of semaphore signaling between ports x Fully asynchronous operation from either port x Battery backup operation2V data retention x TTL-compatible, single 5V (±10%) power supply x Available in 100-pin Thin Quad Flatpack x Industrial temperature range (40°C to +85°C) is available for selected speeds Functional Block Diagram NOTES: 1. (MASTER): BUSY is output; (SLAVE): BUSY is input. 2. BUSY outputs and INT outputs are non-tri-stated push-pull. I/O Control Address Decoder MEMORY ARRAY ARBITRATION INTERRUPT SEMAPHORE LOGIC Address Decoder I/O Control R/ WL BUSYL A11L A0L 4089 drw 01 UBL LBL CEL OEL I/O9L-I/O17L I/O0L-I/O8L CEL OEL R/ WL SEML INTL M/ S R/ WR BUSYR UBR LBR CER OER I/O9R-I/O17R I/O0R-I/O8R A11R A0R R/ WR SEMR INTR CER OER (2) (1,2) (1,2) (2) 13 13 . |
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