1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

Top View

V–

V+

GND

Dual-In-Line

and SOIC

DG611

Top View

V–

V+

NC

NC

GND

LCC

Key

910

11

12

13

4

5

6

7

8

1

2

319

20

14

15

16

17

18

DG611

DG611/612/613

Vishay Siliconix

Document Number: 70057

S-00399—Rev. G, 13-Sep-99

www.vishay.com

S FaxBack 408-970-5600

4-1

High-Speed, Low-Glitch D/CMOS Analog Switches

FEATURES

BENEFITS

APPLICATIONS

D Low Charge Injection: "2 pC

D Wide Bandwidth: 500 MHz

D 5-V CMOS Logic Compatible

D Low Quiescent Power : 1.2 nW

D Single Supply Operation

D Improved Data Throughput

D Minimal Switching Transients

D Improved System Performance

D Easily Interfaced

D Low Insertion Loss

D Minimal Power Consumption

D Fast Sample-and-Holds

D Synchronous Demodulators

D Pixel-Rate Video Switching

D Disk/Tape Drives

D DAC Deglitching

D Switched Capacitor Filters

D GaAs FET Drivers

D Satellite Receivers

DESCRIPTION

The DG611/612/613 feature high-speed low-capacitance

lateral DMOS switches. Charge injection has been minimized

to optimize performance in fast sample-and-hold applications.

Each switch conducts equally well in both directions when on

minimized to ensure fast switching and low-glitch energy. To

achieve such fast and clean switching performance, the

DG611/612/613 are built on the Vishay Siliconix proprietary

D/CMOS process. This process combines n-channel DMOS

switching FETs with low-power CMOS control logic and

drivers. An epitaxial layer prevents latchup.

The DG611 and DG612 differ only in that they respond to

opposite logic levels. The versatile DG613 has two normally

open and two normally closed switches. It can be given various

configurations, including four SPST, two SPDT, one DPDT.

For additional information see Applications Note AN207

(FaxBack number 70605).

FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION

Four SPST Switches per Package

TRUTH TABLE

Logic

DG611

DG612

0

ON

OFF

1

OFF

ON

Logic “0”

v 1 V

Logic “1”

w 4 V