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TCA9539PWR Datasheet(PDF) 29 Page - Texas Instruments |
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TCA9539PWR Datasheet(HTML) 29 Page - Texas Instruments |
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29 / 46 page  VCC Time VCC_GH VCC_GW VCC_MV VCC Ramp-Up Time to Re-Ramp Time Ramp-Down VCC drops below V 50 mV PORF – VCC_RT VCC_FT VCC_TRR 29 TCA9539 www.ti.com SCPS202C – OCTOBER 2009 – REVISED MAY 2016 Product Folder Links: TCA9539 Submit Documentation Feedback Copyright © 2009–2016, Texas Instruments Incorporated (1) TA = –40°C to +85°C (unless otherwise noted) 10 Power Supply Recommendations 10.1 Power-On Reset Requirements In the event of a glitch or data corruption, the TCA9539 can be reset to its default conditions by using the power- on reset feature. Power-on reset requires that the device go through a power cycle to be completely reset. This reset also happens when the device is powered on for the first time in an application. The voltage waveform for a power-on reset is shown in Figure 40. VCC Is lowered below the POR threshold, then ramped back up to VCC Figure 40. Voltage Waveform for Power-On Reset Table 8 specifies the performance of the power-on reset feature for the TCA9539. Table 8. Recommended Supply Sequencing and Ramp Rates (1) PARAMETER MIN TYP MAX UNIT VCC_FT Fall rate See Figure 40 0.1 ms VCC_RT Rise rate See Figure 40 0.1 ms VCC_TRR Time to re-ramp (when VCC drops to VPOR_MIN – 50 mV or when VCC drops to GND) See Figure 40 1 μs VCC_GH The level (referenced to VCC) that VCC can glitch down to, but not cause a functional disruption when VCC_GW See Figure 41 1.2 V VCC_MV The minimum voltage that VCC can glitch down to without causing a reset (VCC_GH must not be violated) See Figure 41 1.5 V VCC_GW Glitch width that will not cause a functional disruption See Figure 41 10 μs VPORF Voltage trip point of POR on falling VCC 0.75 1 V VPORR Voltage trip point of POR on rising VCC 1.2 1.5 V Glitches in the power supply can also affect the power-on reset performance of this device. The glitch width (VCC_GW) and height (VCC_GH) are dependent on each other. The bypass capacitance, source impedance, and device impedance are factors that affect power-on reset performance. Figure 41 and Table 8 provide more information on how to measure these specifications. Figure 41. Glitch Width and Glitch Height |
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