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TAS5110A Datasheet(PDF) 7 Page - Texas Instruments |
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TAS5110A Datasheet(HTML) 7 Page - Texas Instruments |
7 / 20 page TAS5110A SLES079A – APRIL 2003 – REVISED MAY 2003 www.ti.com 7 Control/Sense Circuitry The control/sense circuitry consists of the following 3.3-V logic level pins: PWDN, RESET, ERR0, ERR1, and SHUTDOWN. The active-low PWDN input pin powers down all internal circuitry and forces the H-bridge outputs to the Hi-Z state. When the PWDN pin is low, the open drain ERR0, ERR1, and SHUTDOWN pins are also disabled so that their outputs can be pulled high. The active-low RESET input pin forces the H-bridge outputs to the low-low state and resets the overcurrent shutdown latch. The PWDN pin overrides the RESET pin. The ERR0, ERR1, and SHUTDOWN outputs indicate the following conditions in the TAS5110A as shown in the following table. These three outputs are open-drain connections with internal pullup resistors so that wire-ORed connections can be made by the user with other external control devices. The short-circuit protect error condition latches the TAS5110A in this shutdown state and forces the H-bridge outputs to the Hi-Z state until the device is reset by means of the RESET pin. The illegal PWM input state, overtemperature, and low regulator voltage error conditions does not latch the device in the shutdown condition. Instead the H-bridge outputs are forced to the low-low state and the TAS5110A returns to normal operation as soon as the error condition ends. Loss of clocking PWM signal is also considered an illegal PWM input state. SHUTDOWN ERR1 ERR0 FUNCTION OUTPUTA OUTPUTB 0 0 0 Illegal PWM input state Low Low 0 0 1 Short circuit protect (latch) Hi-Z Hi-Z 0 1 0 Over temperature protect Low Low 0 1 1 Low regulator voltage protect Low Low 1 0 0 Reserved — — 1 0 1 Reserved — — 1 1 0 High temperature – warning Normal Normal 1 1 1 Normaloperation Normal Normal |
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