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LMK04906 Datasheet(PDF) 72 Page - Texas Instruments |
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LMK04906 Datasheet(HTML) 72 Page - Texas Instruments |
72 / 113 page LMK04906 SNAS589D – JUNE 2012 – REVISED MAY 2013 www.ti.com Table 71. DAC_LOW_TRIP, 6 bits R14[11:6] Trip voltage from GND (V) 0 (0x00) 1 × Vcc / 64 1 (0x01) 2 × Vcc / 64 2 (0x02) 3 × Vcc / 64 3 (0x03) 4 × Vcc / 64 4 (0x04) 5 × Vcc / 64 ... ... 61 (0x3D) 62 × Vcc / 64 62 (0x3E) 63 × Vcc / 64 63 (0x3F) 64 × Vcc / 64 EN_VTUNE_RAIL_DET Enables the DAC Vtune rail detection. When the DAC achieves a specified Vtune, if this bit is enabled, the current clock input is considered invalid and an input clock switch event is generated. Table 72. EN_VTUNE_RAIL_DET R14[5] State 0 Disabled 1 Enabled REGISTER 15 MAN_DAC Sets the DAC value when in manual DAC mode in ~3.2 mV steps. Table 73. MAN_DAC, 10 bits R15[31:22] DAC Voltage 0 (0x00) 0 × Vcc / 1023 1 (0x01) 1 × Vcc / 1023 2 (0x02) 2 × Vcc / 1023 ... ... 1023 (0x3FF) 1023 × Vcc / 1023 EN_MAN_DAC This bit enables the manual DAC mode. Table 74. EN_MAN_DAC R15[20] DAC Mode 0 Automatic 1 Manual HOLDOVER_DLD_CNT Lock must be valid for this many clocks of PLL1 PDF before holdover mode is exited. Table 75. HOLDOVER_DLD_CNT, 14 bits R15[19:6] Exit Counts 0 (0x00) Reserved 1 (0x01) 1 2 (0x02) 2 72 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: LMK04906 |
Similar Part No. - LMK04906_15 |
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Similar Description - LMK04906_15 |
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