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LMK04906 Datasheet(PDF) 38 Page - Texas Instruments |
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LMK04906 Datasheet(HTML) 38 Page - Texas Instruments |
38 / 113 page LMK04906 SNAS589D – JUNE 2012 – REVISED MAY 2013 www.ti.com DYNAMICALLY PROGRAMMING DIGITAL DELAY To use dynamic digital delay synchronization qualification set SYNC_QUAL = 1. This causes the SYNC pulse to be qualified by a clock output so that the SYNC event occurs after a specified time from a clock output transition. This allows the relative adjustment of clock output phase in real-time with no or minimum interruption of clock outputs. Hence the term dynamic digital delay. Note that changing the phase of a clock output requires momentarily altering in the rate of change of the clock output phase and therefore by definition results in a frequency distortion of the signal. Without qualifying the SYNC with an output clock, the newly synchronized clocks would have a random and unknown digital delay (or phase) with respect to clock outputs not currently being synchronized. Absolute vs. Relative Dynamic Digital Delay The clock used for qualification of SYNC is selected with the feedback mux (FEEDBACK_MUX). If the clock selected by the feedback mux has its NO_SYNC_CLKoutX = 1, then an absolute dynamic digital delay adjustment will be performed during a SYNC event and the digital delay of the feedback clock will not be adjusted. If the clock selected by the feedback mux has its NO_SYNC_CLKoutX = 0, then a self-referenced or relative dynamic digital delay adjustment will be performed during a SYNC event and the digital delay of the feedback clock will be adjusted. Clocks with NO_SYNC_CLKoutX = 1 always operate without interruption. Dynamic Digital Delay and 0-Delay Mode When using a 0-delay mode absolute dynamic digital delay is recommended. Using relative dynamic digital delay with a 0-delay mode may result in a momentary clock loss on the adjusted clock also being used for 0- delay feedback that may result in PLL1 DLD becoming low. This may result in HOLDOVER mode being activated depending upon device configuration. SYNC and Minimum Step Size The minimum step size adjustment for digital delay is half a clock distribution path cycle. This is achieved by using the CLKoutX_HS bit. The CLKoutX_HS bit change effect is immediate without the need for SYNC. To shift digital delay using CLKoutX_DDLY a SYNC signal must be generated for the change to take effect. Programming Overview To dynamically adjust the digital delay with respect to an existing clock output the device should be programmed as follows: • Set SYNC_QUAL = 1 for clock output qualification. • Set CLKout2_PD = 0. Required for proper operation of SYNC_QUAL = 1. • Set EN_FEEDBACK_MUX = 1 to enable the feedback buffer. • Set FEEDBACK_MUX to the clock output that the newly synchronized clocks will be qualified by. • Set NO_SYNC_CLKoutX = 1 for the output clocks that will continue to operate during the SYNC event. There is no interruption of output on these clocks. – If FEEDBACK_MUX selects a clock output with NO_SYNC_CLKoutX = 1, then absolute dynamic digital delay is performed. – If FEEDBACK_MUX selects a clock output with NO_SYNC_CLKoutX = 0, then self-referenced or relative dynamic digital delay is performed. • The SYNC_EN_AUTO bit may be set to cause a SYNC event to begin when register R0 to R5 is programmed. The auto SYNC feature is a convenience since does not require the application to manually assert SYNC by toggling the SYNC_POL_INV bit or the SYNC pin when changing digital delay. However, under the following condition a special programming sequence is required if SYNC_EN_AUTO = 1: – The CLKoutX_DDLY value being set in the programmed register is 13 or more. • Under the following condition a SYNC_EN_AUTO must = 0: – If the application requires a digital delay resolution of half a clock distribution path cycle in relative dynamic digital delay mode because the HS bit must be fixed per Table 8 for a qualifying clock. 38 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: LMK04906 |
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