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LMH6702J-QMLV Datasheet(PDF) 9 Page - Texas Instruments |
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LMH6702J-QMLV Datasheet(HTML) 9 Page - Texas Instruments |
9 / 17 page LMH6702 + - CIN ADC RS 1 10 100 FREQUENCY (MHz) -90 -80 -70 -60 -50 -40 -30 AV = +2 RL = 100: VO = 2VPP CPOS & CNEG REMOVED CPOS & CNEG INCLUDED LMH6702QML www.ti.com SNOSAQ2E – JULY 2005 – REVISED MARCH 2013 If this lay out technique has not been observed on a particular application board, designer may actually find that supply decoupling caps could adversely affect HD2 performance by increasing the coupling phenomenon already mentioned. Figure 23 below shows actual HD2 data on a board where the ground plane is "shared" between the supply decoupling capacitors and the rest of the circuit. Once these capacitors are removed, the HD2 distortion levels reduce significantly, especially between 10MHz-20MHz, as shown in Figure 23 below: Figure 23. Decoupling Current Adverse Effect on a Board with Shared Ground Plane At these extremely low distortion levels, the high frequency behavior of decoupling capacitors themselves could be significant. In general, lower value decoupling caps tend to have higher resonance frequencies making them more effective for higher frequency regions. A particular application board which has been laid out correctly with ground returns "split" to minimize coupling, would benefit the most by having low value and higher value capacitors paralleled to take advantage of the effective bandwidth of each and extend low distortion frequency range. CAPACITIVE LOAD DRIVE Figure 24 shows a typical application using the LMH6702 to drive an ADC. Figure 24. Input Amplifier to ADC The series resistor, RS, between the amplifier output and the ADC input is critical to achieving best system performance. This load capacitance, if applied directly to the output pin, can quickly lead to unacceptable levels of ringing in the pulse response. The plot of "RS and Settling Time vs. CL" in the Typical Performance Characteristics section is an excellent starting point for selecting RS. The value derived in that plot minimizes the step settling time into a fixed discrete capacitive load with the output driving a very light resistive load (1k Ω). Sensitivity to capacitive loading is greatly reduced once the output is loaded more heavily. Therefore, for cases where the output is heavily loaded, RS value may be reduced. The exact value may best be determined experimentally for these cases. Copyright © 2005–2013, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Links: LMH6702QML |
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