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U634H256D1M45 Datasheet(PDF) 5 Page - Zentrum Mikroelektronik Dresden AG |
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U634H256D1M45 Datasheet(HTML) 5 Page - Zentrum Mikroelektronik Dresden AG |
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5 / 14 page  5 April 21, 2004 U634H256 Read Cycle 1: Ai-controlled (during Read cycle: E = G = VIL, W = VIH)f Read Cycle 2: G-, E-controlled (during Read cycle: W = VIH)g No. Switching Characteristics Write Cycle Symbol 25 35 45 Unit Alt. #1 Alt. #2 IEC Min. Max. Min. Max. Min. Max. 12 Write Cycle Time tAVAV tAVAV tcW 25 35 45 ns 13 Write Pulse Width tWLWH tw(W) 20 25 30 ns 14 Write Pulse Width Setup Time tWLEH tsu(W) 20 25 30 ns 15 Address Setup Time tAVWL tAVEL tsu(A) 00 0 ns 16 Address Valid to End of Write tAVWH tAVEH tsu(A-WH) 20 25 30 ns 17 Chip Enable Setup Time tELWH tsu(E) 20 25 30 ns 18 Chip Enable to End of Write tELEH tw(E) 20 25 30 ns 19 Data Setup Time to End of Write tDVWH tDVEH tsu(D) 10 12 15 ns 20 Data Hold Time after End of Write tWHDX tEHDX th(D) 00 0 ns 21 Address Hold after End of Write tWHAX tEHAX th(A) 00 0 ns 22 W LOW to Output in High-Zh, i tWLQZ tdis(W) 10 13 15 ns 23 W HIGH to Output in Low-Z tWHQX ten(W) 55 5 ns ta(A) Previous Data Valid Output Data Valid tcR Address Valid tv(A) Ai (1) (2) (9) Ai E G tdis(E) tcR ta(E) ten(E) ten(G) ta(G) tdis(G) Output Data Valid High Impedance ICC ACTIVE STANDBY tPD tPU (1) (3) (4) (5) (7) (6) (8) (10) (11) ta(A) (2) Address Valid DQi Output DQi Output |
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