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U634H256SM25 Datasheet(PDF) 11 Page - Zentrum Mikroelektronik Dresden AG |
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U634H256SM25 Datasheet(HTML) 11 Page - Zentrum Mikroelektronik Dresden AG |
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11 / 14 page  11 April 21, 2004 U634H256 Device Operation The U634H256 has two separate modes of operation: SRAM mode and nonvolatile mode. The memory ope- rates In SRAM mode as a standard fast static RAM. Data is transferred in nonvolatile mode from SRAM to EEPROM (the STORE operation) or from EEPROM to SRAM (the RECALL operation). In this mode SRAM functions are disabled. STORE cycles may be initiated under user control via a software sequence or HSB assertion and are also auto- matically initiated when the power supply voltage level of the chip falls below VSWITCH. RECALL operations are automatically initiated upon power up and may also occur when the VCCX rises above VSWITCH, after a low power condition. RECALL cycles may also be initiated by a software sequence. SRAM READ The U634H256 performs a READ cycle whenever E and G are LOW and HSB and W are HIGH. The address specified on pins A0 - A14 determines which of the 32768 data bytes will be accessed. When the READ is initiated by an address transition, the outputs will be valid after a delay of tcR. If the READ is initiated by E or G, the outputs will be valid at ta(E) or at ta(G), whichever is later. The data outputs will repeatedly respond to address changes within the tcR access time without the need for transition on any control input pins, and will remain valid until another address change or until E or G is brought HIGH or W or HSB is brought LOW. SRAM WRITE A WRITE cycle is performed whenever E and W are LOW and HSB is HIGH. The address inputs must be stable prior to entering the WRITE cycle and must remain stable until either E or W goes HIGH at the end of the cycle. The data on pins DQ0 - 7 will be written into the memory if it is valid tsu(D) before the end of a W controlled WRITE or tsu(D) before the end of an E con- trolled WRITE. It is recommended that G is kept HIGH during the entire WRITE cycle to avoid data bus contention on the common I/O lines. If G is left LOW, internal circuitry will turn off the output buffers tdis(W) after W goes LOW. Automatic STORE During normal operation, the U634H256 will draw cur- rent from VCCX to charge up a capacitor connected to the VCAP pin. This stored charge will be used by the chip to perform a single STORE operation. If the voltage on the VCCX pin drops below VSWITCH, the part will automatically disconnect the VCAP pin from VCCX and initiate a STORE operation. Figure 1 shows the proper connection of capacitors for automatic STORE operation. The charge storage capa- citor should have a capacity of 100 µF ( ± 20 %) at 6 V. Each U634H256 must have its own 100 µF capacitor. Each U634H256 must have a high quality, high fre- quency bypass capacitor of 0.1 µF connected between VCAP and VSS, using leads and traces that are short as possible. This capacitor do not replace the normal expected high frequency bypass capacitor between the power supply voltage and VSS. In order to prevent unneeded STORE operations, auto- matic STOREs as well as those initiated by externally driving HSB LOW will be ignored unless at least one WRITE operation has taken place since the most recent STORE cycle. Note that if HSB is driven LOW via external circuitry and no WRITES have taken place, the part will still be disabled until HSB is allowed to return HIGH. Software initiated STORE cycles are per- formed regardless of whether or not a WRITE opera- tion has taken place. Automatic RECALL During power up, an automatic RECALL takes place. At a low power condition (power supply voltage < VSWITCH) an internal RECALL request may be latched. As soon as power supply voltage exceeds the sense voltage of VSWITCH, a requested RECALL cycle will automatically be initiated and will take tRESTORE to complete. If the U634H256 is in a WRITE state at the end of power up RECALL, the SRAM data will be corrupted. To help avoid this situation, a 10 k Ω resistor should be connected between W and power supply voltage. Software Nonvolatile STORE The U634H256 software controlled STORE cycle is initiated by executing sequential READ cycles from six specific address locations. By relying on READ cycles only, the U634H256 implements nonvolatile operation while remaining compatible with standard 32K x 8 SRAMs. During the STORE cycle, an erase of the pre- vious nonvolatile data is performed first, followed by a parallel programming of all nonvolatile elements. Once a STORE cycle is initiated, further inputs and outputs are disabled until the cycle is completed. Because a sequence of addresses is used for STORE initiation, it is important that no other READ or WRITE accesses intervene in the sequence or the sequence will be aborted. To initiate the STORE cycle the following READ sequence must be performed: |
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