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PCM3008T Datasheet(PDF) 8 Page - Texas Instruments |
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PCM3008T Datasheet(HTML) 8 Page - Texas Instruments |
8 / 30 page PCM3008 SLAS332 – APRIL 2001 8 www.ti.com system clock (continued) Table 1. System Clock Frequencies SAMPLING RATE FREQUENCY SYSTEM CLOCK FREQUENCY (MHz) (kHz) 256fs 384fs 512fs 32.0 8.1920 12.2880 16.3840 44.1 11.2896 16.9340 22.5792 48.0 12.2880 18.4320 24.5760 reset The ADC and DAC portions of the PCM3008 can be reset simultaneously by the power down control pins, PDAD and PDDA. This external reset using PDAD and PDDA must be always done at least once after the power is applied. Internal state is kept in reset during PDAD = low and PDDA = low and for 1024 system clock counts after PDAD = high or PDDA = high, and then the initialization sequence for ADC and DAC is started. For the ADC, DOUT is kept in ZERO during the initialization sequence and DOUT outputs normal data corresponding to the input analog signal after tADCDLY1. In the case of the DAC, the fade-in function is started, the signal level on VOUT increases gradually and reaches to full level corresponding to the input digital signal after tDACDLY1. The following figure illustrates the reset timing for power-on and the ADC/DAC output response for the power-on and reset sequence. |
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