Electronic Components Datasheet Search |
|
PCM56UG4 Datasheet(PDF) 8 Page - Texas Instruments |
|
PCM56UG4 Datasheet(HTML) 8 Page - Texas Instruments |
8 / 16 page 8 ® PCM56 SECOND GENERATION SYSTEMS One method of avoiding the problems associated with a higher order analog filter would be to use digital filter oversampling techniques. Oversampling by a factor of two would move the sampling frequency (88.2kHz) out to a point where only a simple low-order phase-linear analog filter is required after the deglitcher output to remove unwanted intermodulation products. In a digital compact disc application, various VLSI chips perform the functions of error detection/correction, digital filtering, and formatting of the digital information to provide the clock, latch enable, and serial input to the PCM56. These VLSI chips are available from several sources (Sony, Yamaha, Signetics, etc.) and are specifically optimized for digital audio applications. Oversampled circuitry requires a very fast D/A converter since the sampling frequency is multiplied by a factor of two or more (for each output channel). A single PCM56 can provide two-channel oversampling at a 4X rate (176.4kHz/ channel) and still remain well within the settling time requirements for maintaining specified THD performance. This would reduce the complexities of the analog filter even further from that used in 2X oversampling circuitry. FIGURE 9. A Sample/Hold Amplifier (Deglitcher) is Required at the Digital-to-Analog Output for Both Left and Right Channels. FIGURE 10. Timing Diagram for the Deglitcher Control Signals. R 2 2.2k Ω A 1 (1) C 1 680pF C B A Left Channel Output to LPF SW 1 MP7512 (Micro Power) R 4 2.2k Ω A 2 (1) C 2 680pF C B A Right Channel Output to LPF SW 2 MP7512 (Micro Power) R 1 2.2k Ω R 3 2.2k Ω NOTE: (1) 1 OPA101AM or 1/4 OPA404KP or 1 OPA606KP or OPA2604. PCM56 Serial Data Clock Latch Enable Left Channel Deglitcher Control Right Channel Deglitcher Control A "low" signal on the deglitcher control closes switch "A", while a "high" signal closes switch "B". Latch Enable Right Channel Serial Data 44.1kHz Left Channel Left Channel Right Channel Right Channel Deglitcher Control Left Channel Deglitcher Control t DELAY 4.5µs max t = 1.5µs DAC Settling Time ω The deglitcher control signals by timing control logic. The fast settling time of the PCM56 makes it possible to minimize the delay between left and right channels to about 4.5µs, which reduces phase error at the higher audio frequencies. |
Similar Part No. - PCM56UG4 |
|
Similar Description - PCM56UG4 |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.COM |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |