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PI4MSD5V9545A Datasheet(PDF) 6 Page - Pericom Semiconductor Corporation |
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PI4MSD5V9545A Datasheet(HTML) 6 Page - Pericom Semiconductor Corporation |
6 / 13 page ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| 2015-07-0036 PT0526-4 8/18/15 6 PI4MSD5V9545A 4 Channel I2C bus Switch with Interrupt Logic and Reset I2C Interface Timing Requirements Symbol Parameter STANDARD MODE I2C BUS FAST MODE I2C BUS UNIT MIN MAX MIN MAX fscl I2C clock frequency 0 100 0 400 kHz tLow I2C clock high time 4.7 1.3 μs tHigh I2C clock low time 4 0.6 μs tSP I2C spike time 50 50 ns tSU:DAT I2C serial-data setup time 250 100 ns tHD:DAT I2C serial-data hold time 0 [1] 0 [1] μs tr I2C input rise time 1000 300 ns tf I2C input fall time 300 300 ns tBUF I2C bus free time between stop and start 4.7 1.3 μs tSU:STA I2C start or repeated start condition setup 4.7 0.6 μs tHD:STA I2C start or repeated start condition hold 4 0.6 μs tSU:STO I2C stop condition setup 4 0.6 μs tVD:DAT Valid-data time (high to low) [2] SCL low to SDA output low valid 1 1 μs Valid-data time (low to high) [2] SCL low to SDA output high valid 0.6 0.6 μs tVD:ACK Valid-data time of ACK condition ACK signal from SCL low to SDA output low 1 1 μs Cb I2C bus capacitive load 400 400 pF Notes: [1] A device internally must provide a hold time of at least 300 ns for the SDA signal (referred to as the VIH min of the SCL signal), in order to bridge the undefined region of the falling edge of SCL. [2] Data taken using a 1-kΩ pullup resistor and 50-pF load Notes Figure 2. Definition of timing on the I2C-bus |
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