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SN74SSTV16857DGVRG Datasheet(PDF) 1 Page - Texas Instruments

Part # SN74SSTV16857DGVRG
Description  14-BIT REGISTERED BUFFER WITH SSTL_2 INPUTS AND OUTPUTS
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

SN74SSTV16857DGVRG Datasheet(HTML) 1 Page - Texas Instruments

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SN74SSTV16857
14BIT REGISTERED BUFFER
WITH SSTL_2 INPUTS AND OUTPUTS
SCES344E – DECEMBER 2000 – REVISED NOVEMBER 2002
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D Member of the Texas Instruments
Widebus
 Family
D Supports SSTL_2 Data Inputs
D Outputs Meet SSTL_2 Class II
Specifications
D Differential Clock (CLK and CLK) Inputs
D Supports LVCMOS Switching Levels on the
RESET Input
D RESET Input Disables Differential Input
Receivers, Resets All Registers, and
Forces All Outputs Low
D Flow-Through Architecture Optimizes PCB
Layout
D Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
D ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
description
This 14-bit registered buffer is designed for 2.3-V
to 2.7-V VCC operation.
All inputs are SSTL_2, except the LVCMOS reset
(RESET) input. All outputs are SSTL_2, Class II
compatible.
The SN74SSTV16857 operates from a differential clock (CLK and CLK). Data are registered at the crossing
of CLK going high and CLK going low.
The device supports low-power standby operation. When RESET is low, the differential input receivers are
disabled and undriven (floating) data, clock, and reference voltage (VREF) inputs are allowed. In addition, when
RESET is low, all registers are reset and all outputs are forced low. The LVCMOS RESET input always must
be held at a valid logic high or low level.
To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in
the low state during power up.
ORDERING INFORMATION
TA
PACKAGE†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
0
°C to 70°C
TSSOP – DGG
Tape and reel
SN74SSTV16857DGGR
SSTV16857
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Copyright
 2002, Texas Instruments Incorporated
Widebus is a trademark of Texas Instruments.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
DGG PACKAGE
(TOP VIEW)
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Q1
Q2
GND
VDDQ
Q3
Q4
Q5
GND
VDDQ
Q6
Q7
VDDQ
GND
Q8
Q9
VDDQ
GND
Q10
Q11
Q12
VDDQ
GND
Q13
Q14
D1
D2
GND
VCC
D3
D4
D5
D6
D7
CLK
CLK
VCC
GND
VREF
RESET
D8
D9
D10
D11
D12
VCC
GND
D13
D14
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Not Recommended for New Designs


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SN74SSTV16857DGVR TI-SN74SSTV16857DGVR Datasheet
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[Old version datasheet]   14-BIT REGISTERED BUFFER WITH SSTL 2 INPUTS AND OUTPUTS
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