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SN74SSTV16857DGVRG Datasheet(PDF) 4 Page - Texas Instruments

Part # SN74SSTV16857DGVRG
Description  14-BIT REGISTERED BUFFER WITH SSTL_2 INPUTS AND OUTPUTS
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

SN74SSTV16857DGVRG Datasheet(HTML) 4 Page - Texas Instruments

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SN74SSTV16857
14BIT REGISTERED BUFFER
WITH SSTL_2 INPUTS AND OUTPUTS
SCES344E – DECEMBER 2000 – REVISED NOVEMBER 2002
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 1)
VCC = 2.5 V
± 0.2 V†
UNIT
MIN
MAX
UNIT
fclock
Clock frequency
200
MHz
tw
Pulse duration
CLK, CLK high or low
2.5
ns
tact
Differential inputs active time (see Note 5)
22
ns
tinact
Differential inputs inactive time (see Note 6)
22
ns
t
Set p time
Fast slew rate (see Notes 7 and 9)
Dt bf
CLK
↑ CLK↓
0.75
ns
tsu
Setup time
Slow slew rate (see Notes 8 and 9)
Data before CLK
↑, CLK↓
0.9
ns
t
Hold time
Fast slew rate (see Notes 7 and 9)
D t
ft
CLK
↑ CLK↓
0.75
ns
th
Hold time
Slow slew rate (see Notes 8 and 9)
Data after CLK
↑, CLK↓
0.9
ns
† For this test condition, VDDQ always is equal to VCC.
NOTES:
5. Data inputs must be held low for a minimum time of tact min, after RESET is taken high.
6. Data and clock inputs must be held at valid levels (not floating) for a minimum time of tinact min, after RESET is taken low.
7. Data signal input slew rate
≥1 V/ns
8. Data signal input slew rate
≥0.5 V/ns and <1 V/ns
9. CLK, CLK input slew rates are
≥1 V/ns.
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 2.5 V
± 0.2 V†
UNIT
PARAMETER
(INPUT)
(OUTPUT)
MIN
MAX
UNIT
fmax
200
MHz
tpd
CLK and CLK
Q
1.1
2.8
ns
tPHL
RESET
Q
5
ns
† For this test condition, VDDQ always is equal to VCC.
Not Recommended for New Designs


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Texas Instruments
SN74SSTV16857DGVR TI-SN74SSTV16857DGVR Datasheet
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[Old version datasheet]   14-BIT REGISTERED BUFFER WITH SSTL 2 INPUTS AND OUTPUTS
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