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LM98640 Datasheet(PDF) 9 Page - Texas Instruments |
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LM98640 Datasheet(HTML) 9 Page - Texas Instruments |
9 / 46 page LM98640 www.ti.com SNAS596A – JUNE 2012 – REVISED MAY 2013 LM98640 Electrical Characteristics (1) (continued) The following specifications apply for VDD33 = 3.3V, VDD18 = 1.8V, CL = 10 pF, and fINCLK = 40 MHz unless otherwise specified. Boldface limits apply for TA = TMIN to TMAX; all other limits TA = 25°C. Symbol Parameter Conditions Typical(2) Min Max Units Power Supply Specifications Powerdown Control Reg = 0x00 (see Power Trimming section for PGA and ADC Power Trimming register settings) 5 MHz 51.5 15 MHz 61.3 mA 25 MHz 69.6 40 MHz 87.6 Powerdown Control Reg = 0x00 (see Power Trimming section for PGA and ADC Power Trimming VDD33 Analog Supply Current register settings) Dual Channel Power optimized for 5 MHz 51.5 PGA Gain = 1-8x 15 MHz 61.3 mA 25 MHz 72.9 40 MHz 91.3 103 Powerdown Control Reg = 0x15 (CH1 PD) or IA = 0x2A (CH2 PD) (see Power Trimming section for PGA and ADC Power Trimming register settings) 5 MHz 29.5 15 MHz 36.1 mA 25 MHz 42 40 MHz 53.7 Powerdown Control Reg = 0x15 (CH1 PD) or = 0x2A (CH2 PD) (see Power Trimming section for VDD33 Analog Supply Current PGA and ADC Power Trimming Single Channel register settings) Power optimized for 5 MHz 29.5 PGA Gain = 1-8x 15 MHz 36.1 mA 25 MHz 43.8 40 MHz 55.6 64 VDD33 Analog Supply Current Powerdown Control Reg 2.85 3.85 mA Powerdown = 0x80 5 MHz 36 VDD18 Digital Supply Current 15 MHz 39 LVDS Quad Lane Mode mA LVDS Output Mode Reg 25 MHz 42 = 0x0E 40 MHz 45 5 MHz 23.5 ID 15 MHz 25.5 VDD18 Digital Supply Current mA 25 MHz 27.5 40 MHz 30.5 37 VDD18 Digital Supply Current Powerdown Control 1.2 3.0 mA Powerdown Reg = 0x80 Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Links: LM98640 |
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