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LM96551 Datasheet(PDF) 8 Page - Texas Instruments |
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LM96551 Datasheet(HTML) 8 Page - Texas Instruments |
8 / 17 page VPP 0 Output NINx PINx 50% 50% 50% tdr tdf 50% VPP 90% 0 tr Output 10% NINx PINx 90% 10% tf LM96551 SNAS511B – OCTOBER 2011 – REVISED MAY 2013 www.ti.com Continuous-wave (CW) applications are supported for low power consumption down to VPP = -VNN = 3.3V with Mode =HI. Internally, the CMOS logic input signals are level shifted to VDD = 10V and VDN = -10V for pulse transmission. The outputs of the level shifter drive the high-voltage P and N drivers that control the output power MOSFETs, which are supplied from the positive and negative rails VPP and VNN, respectively. The high-voltage rails are designed for a maximum of 50V; however, they can be operated down to 3.3V. The necessary gate-overdrive voltage levels for the output drivers are internally generated from the high-voltage rails. Over-Temperature Protection (OTP) is implemented by continuously monitoring the on-chip temperature. The OTP output (open drain) pin goes LO when the chip temperature exceeds a critical level. Prior to this event, the user must ensure that the chip is powered down before fatal damage occurs. In addition to a primary software controlled safety shutdown, the OTP pin can be also be hard-wired to the EN pin as a secondary safety measure. Timing Diagrams RISE AND FALL TIME The timing diagram shown in Figure 4 defines the rise and fall times tr and tf. Figure 4. Timing Diagram Defining Rise and Fall Times tr and tf, respectively INPUT TO OUTPUT DELAY The timing diagram shown in Figure 5 defines the delays between the input and output signals. Figure 5. Timing Diagram Defining Input-to-Output Delays Times 8 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LM96551 |
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