Specifications ispLSI 2032E

9

ispLSI 2032E Timing Model

Derivations of

=

=

=

=

Logic + Reg su - Clock (min)

(

(#20 + #22 + #26) + (#29) - (#20 + #22 + #35)

(0.6 + 0.7 + 2.2) + (0.8) - (0.6 + 0.7 + 0.3)

=

=

=

=

Clock (max) + Reg h - Logic

(

(#20 + #22 + #35) + (#30) - (#20 + #22 + #26)

(0.6 + 0.7 + 2.8) + (1.7) - (0.6 + 0.7 + 2.2)

=

=

=

=

Clock (max) + Reg co + Output

(

(#20 + #22 + #35) + (#31) + (#36 + #38)

(0.6 + 0.7 + 2.8) + (0.7) + (1.0 + 1.0)

Table 2-0042/2032E

Note: Calculations are based upon timing specifications for the ispLSI 2032E-225L

2.7

2.3

6.8

GLB Reg

Delay

I/O Pin

(Output)

ORP

Delay

Feedback

Reg 4 PT Bypass

20 PT

XOR Delays

Control

PTs

I/O Pin

(Input)

Y0,1,2

GRP

GLB Reg Bypass

ORP Bypass

DQ

RST

RE

OE

CK

I/O Delay

I/O Cell

ORP

GLB

GRP

I/O Cell

#24

#25, 26, 27

#33, 34,

35

#43, 44

#36

Reset

Ded. In

#21

#20

#28

#29, 30,

31, 32

#38,

#39

GOE 0

#42

#40, 41

0491/2032E

#22

Comb 4 PT Bypass #23

#37

#45