Specifications ispLSI 2032E

5

External Timing Parameters

Over Recommended Operating Conditions

UNITS

-200

MIN.

TEST

COND.

1. Unless noted otherwise, all parameters use a GRP load of four GLBs, 20 PTXOR path, ORP and Y0 clock.

2. Refer to Timing Model in this data sheet for further details.

3. Standard 16-bit counter using GRP feedback.

4. Reference Switching Test Conditions section.

Table 2-0030A/2032E

1

1

tsu2 + tco1

(

)

-180

MIN.

MAX.

MAX.

DESCRIPTION

#

2

4

PARAMETER

A1

Data Prop. Delay, 4PT Bypass, ORP Bypass

–

3.5

–

5.0

ns

A2

Data Prop. Delay

–

–

ns

A3

200

–

180

–

MHz

–4

Clk Frequency with Ext. Feedback

–

–

MHz

–5

Clk Frequency, Max. Toggle

–

–

MHz

–6

GLB Reg. Setup Time before Clk, 4 PT Bypass

–

–

ns

A7

GLB Reg. Clk to Output Delay, ORP Bypass

–

–

ns

–8

GLB Reg. Hold Time after Clk, 4 PT Bypass

0.0

–

ns

–9

GLB Reg. Setup Time before Clk

3.5

–

ns

–10 GLB Reg. Clk to Output Delay

–

–

ns

–11 GLB Reg. Hold Time after Clk

0.0

–

ns

A12 Ext. Reset Pin to Output Delay, ORP Bypass

–

–

ns

–13 Ext. Reset Pulse Duration

3.5

–

ns

B14 Input to Output Enable

–

–

ns

C15 Input to Output Disable

–

–

ns

B16 Global OE Output Enable

–

–

ns

C17 Global OE Output Disable

–

–

ns

–18 Ext. Synch. Clk Pulse Duration, High

2.0

–

–

ns

–19 Ext. Synch. Clk Pulse Duration, Low

2.0

–

–

ns

167

250

2.5

2.5

–

–

3.5

–

5.0

–

7.0

7.0

3.5

3.5

5.5

-225

MIN. MAX.

–

3.5

–

225

–

–

–

–

–

0.0

3.5

–

0.0

–

3.5

–

–

–

–

2.0

–

2.0

–

167

250

2.5

2.5

–

–

3.5

–

5.0

–

7.0

7.0

3.5

3.5

5.5

125

200

3.0

0.0

4.0

0.0

4.0

2.5

2.5

7.5

4.0

4.5

6.5

10.0

10.0

5.0

5.0