SN54LVT16543, SN74LVT16543

3.3V ABT 16BIT REGISTERED TRANSCEIVERS

WITH 3STATE OUTPUTS

SCBS148C − MAY 1992 − REVISED JULY 1995

1

POST OFFICE BOX 655303

POST OFFICE BOX 1443

Technology (ABT) Design for 3.3-V

Operation and Low-Static Power

Dissipation

Widebus

 Family

Down to 2.7 V

MIL-STD-883C, Method 3015; Exceeds

200 V Using Machine Model

(C = 200 pF, R = 0)

Per JEDEC Standard JESD-17

for External Pullup Resistors

Minimizes High-Speed Switching Noise

PCB Layout

Shrink Small-Outline (DL) and Thin Shrink

Small-Outline (DGG) Packages and 380-mil

Fine-Pitch Ceramic Flat (WD) Package

Using 25-mil Center-to-Center Spacings

description

capability to provide a TTL interface to a 5-V system environment. These devices can be used as two 8-bit

transceivers or one 16-bit transceiver. Separate latch-enable (LEAB or LEBA) and output-enable (OEAB or

OEBA) inputs are provided for each register to permit independent control in either direction of data flow.

The A-to-B enable (CEAB) input must be low in order to enter data from A or to output data from B. If CEAB

is low and LEAB is low, the A-to-B latches are transparent; a subsequent low-to-high transition of LEAB puts

the A latches in the storage mode. With CEAB and OEAB both low, the 3-state B outputs are active and reflect

the data present at the output of the A latches. Data flow from B to A is similar but requires using the CEBA,

LEBA, and OEBA inputs.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

Copyright

 1995, Texas Instruments Incorporated

UNLESS OTHERWISE NOTED this document contains PRODUCTION

DATA information current as of publication date. Products conform to

specifications per the terms of Texas Instruments standard warranty.

Production processing does not necessarily include testing of all

parameters.

Widebus is a trademark of Texas Instruments Incorporated.

SN54LVT16543 . . . WD PACKAGE

SN74LVT16543 . . . DGG OR DL PACKAGE

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1OEAB

1LEAB

1CEAB

GND

1A1

1A2

1A3

1A4

1A5

GND

1A6

1A7

1A8

2A1

2A2

2A3

GND

2A4

2A5

2A6

2A7

2A8

GND

2CEAB

2LEAB

2OEAB

1OEBA

1LEBA

1CEBA

GND

1B1

1B2

1B3

1B4

1B5

GND

1B6

1B7

1B8

2B1

2B2

2B3

GND

2B4

2B5

2B6

2B7

2B8

GND

2CEBA

2LEBA

2OEBA

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.