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SN54LV574A Datasheet(PDF) 2 Page - Texas Instruments |
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SN54LV574A Datasheet(HTML) 2 Page - Texas Instruments |
2 / 23 page SN54LV574A, SN74LV574A OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS SCLS412I − APRIL 1998 − REVISED APRIL 2005 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 description/ordering information (continued) The ’LV574A devices are octal edge-triggered D-type flip-flops designed for 2-V to 5.5-V VCC operation. These devices feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. The devices are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels set up at the data (D) inputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components. OE does not affect the internal operations of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. terminal assignments 1234 A 1D OE VCC 1Q B 3D 3Q 2D 2Q C 5D 4D 5Q 4Q D 7D 7Q 6D 6Q E GND 8D CLK 8Q FUNCTION TABLE (each flip-flop) INPUTS OUTPUT OE CLK D OUTPUT Q L ↑ H H L ↑ LL L H or L X Q0 H X X Z GQN PACKAGE (TOP VIEW) 1 234 A B C D E |
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