XRA1206

4

8-BIT I2C/SMBUS GPIO EXPANDER WITH INTEGRATED LEVEL SHIFTERS

REV. 1.0.0

1.0 FUNCTIONAL DESCRIPTIONS

1.1

interface consists of two lines: serial data (SDA) and serial clock (SCL). In the Standard-mode, the serial clock

and serial data can go up to 100 kbps and in the Fast-mode, the serial clock and serial data can go up to 400

kbps.

HIGH), 7-bit slave address and whether it is a read or write transaction. The next byte is the sub-address that

contains the address of the register to access. The XRA1206 responds to each write with an acknowledge

master contains a stop bit (SDA transition from LOW to HIGH when SCL is HIGH). See Figures 3 - 5 below.

SDA

SCL

S

P

START condition

STOP condition

SW

A

A

AP

SL AVE

AD D R ESS

CO M M A ND

BYT E

DA T A

BYT E

W h ite b lock: h o st to X R A 1 20 x

G rey block: X R A 12 0 x to h ost

SW

A

AR

SLAVE

ADDRESS

COMMAND

BYTE

White block: host to XRA120x

Grey block: XRA120x to host

A

S

SLAVE

ADDRESS

nDATA

ANA

P

LAST DATA

2