XRA1202/1202P

7

REV. 1.0.1

8-BIT I2C/SMBUS GPIO EXPANDER WITH RESET

1.2

Interrupts

The table below summarizes the interrupt behavior of the different register settings for the XRA1202/1202P.

GCR

IER

REIR

FEIR

IFR

1

0

X

X

X

No interrupts enabled (default)

N/A

1

1

0

0

0

A rising or falling edge on the input

Reading the GSR register or if the input

changes back to its previous state (state of

input during last read to GSR)

1

A rising or falling edge on the input and

remains in the new state for more than

1075ns

1

1

1

0

0

A rising edge on the input

Reading the GSR register

1

A rising edge on the input and remains high

for more than 1075ns

1

1

0

1

0

A falling edge on the input

Reading the GSR register

1

A falling edge on the input and remains low

for more than 1075ns

1

1

1

1

0

A rising or falling edge on the input

Reading the GSR register

1

A rising or falling edge on the input and

remains in the new state for more than

1075ns

0

x

x

x

x

No interrupts in output mode

N/A