UT62256C datasheet(3/12 Pages) ETC

Part #	UT62256C

Description	32K X 8 BIT LOW POWER CMOS SRAM

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UTRON

UT62256C

Rev. 1.0

32K X 8 BIT LOW POWER CMOS SRAM

_____________________________________________________________________________________________

UTRON TECHNOLOGY INC.

P80027

1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.

TEL: 886-3-5777882

FAX: 886-3-5777919

3



CAPACITANCE (TA=25℃, f=1.0MHz)

PARAMETER

SYMBOL

MIN.

MAX

UNIT

Input Capacitance

CIN

-

8

pF

Input/Output Capacitance

CI/O

-

10

pF

Note : These parameters are guaranteed by device characterization, but not production tested.

AC TEST CONDITIONS

Input Pulse Levels

0V to 3.0V

Input Rise and Fall Times

5ns

Input and Output Timing Reference Levels

1.5V

Output Load

CL = 100pF, IOH/IOL = -1mA/4mA

AC ELECTRICAL CHARACTERISTICS (VCC = 5V±10% , TA = 0℃ to 70℃)

(1) READ CYCLE

PARAMETER

SYMBOL

UT62256C-35

UT62256C-70

UNIT

MIN.

MAX.

MIN.

MAX.

Read Cycle Time

tRC

35

-

70

-

ns

Address Access Time

tAA

-

35

-

70

ns

Chip Enable Access Time

tACE

-

35

-

70

ns

Output Enable Access Time

tOE

-

25

-

35

ns

Chip Enable to Output in Low Z

tCLZ*

10

-

10

-

ns

Output Enable to Output in Low Z

tOLZ*

5

-

5

-

ns

Chip Disable to Output in High Z

tCHZ*

-

25

-

35

ns

Output Disable to Output in High Z

tOHZ*

-

25

-

35

ns

Output Hold from Address Change

tOH

5

-

5

-

ns

(2) WRITE CYCLE

PARAMETER

SYMBOL

UT62256C-35

UT62256C-70

UNIT

MIN.

MAX.

MIN.

MAX.

Write Cycle Time

tWC

35

-

70

-

ns

Address Valid to End of Write

tAW

30

-

60

-

ns

Chip Enable to End of Write

tCW

30

-

60

-

ns

Address Set-up Time

tAS

0

-

0

-

ns

Write Pulse Width

tWP

25

-

50

-

ns

Write Recovery Time

tWR

0

-

0

-

ns

Data to Write Time Overlap

tDW

20

-

30

-

ns

Data Hold from End of Write Time

tDH

0

-

0

-

ns

Output Active from End of Write

tOW*

5

-

5

-

ns

Write to Output in High Z

tWHZ*

-

15

-

25

ns

*These parameters are guaranteed by device characterization, but not production tested.

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