XR28V382

10

3.3V DUAL LPC UART WITH 128-BYTE FIFO

REV. 1.0.1

1.4.2

Transmitter

The transmitter section comprises of an 8-bit Transmit Shift Register (TSR) and up to 128 bytes of FIFO which

includes a byte-wide Transmit Holding Register (THR). TSR shifts out every data bit with the internal sampling

clock. The transmitter sends the start bit followed by the number of data bits, inserts the proper parity bit if

enabled, and adds the stop bit(s). The status of the THR and TSR are reported in the Line Status Register

(LSR bit-5 and bit-6).

1.4.2.1

Transmit Holding Register (THR) - Write Only

The transmit holding register is an 8-bit register providing a data interface to the host processor. The host

writes transmit data byte to the THR to be converted into a serial data stream including start bit, data bits,

parity bit and stop bit(s). The least significant bit (Bit-0) becomes first data bit to go out. The THR is the input

register to the transmit FIFO of up to 128 bytes when FIFO operation is enabled by FCR bit-0. Every time a

write operation is made to the THR, the FIFO data pointer is automatically bumped to the next sequential data

location.

1.4.2.2

Transmitter Operation in non-FIFO Mode

The host loads transmit data to THR one character at a time. The THR empty flag (LSR bit-5) is set when the

data byte is transferred to TSR. THR flag can generate a transmit empty interrupt (ISR bit-1) when it is enabled

by IER bit-1. The TSR flag (LSR bit-6) is set when TSR becomes completely empty.

Transmit

Holding

Register

(THR)

Transmit Shift Register (TSR)

Data

Byte

L

S

B

M

S

B

THR Interrupt (ISR bit-1)

Enabled by IER bit-1

TXNOFIFO1

Clock