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SAA7724H Datasheet(PDF) 63 Page - NXP Semiconductors |
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SAA7724H Datasheet(HTML) 63 Page - NXP Semiconductors |
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63 / 84 page  2003 Nov 18 63 Philips Semiconductors Preliminary specification Car radio digital signal processor SAA7724H 11.3 Reset initialization With a synchronous reset the SAA7724H will turn to their idle position (state 0), the address counter is set to zero and the SDA_OUT line remains high-impedance. For the SDA line an asynchronous reset is also implemented which is connected directly to the RESET pin. During the asynchronous reset period the internal SDA_OUT line remains HIGH which results in a high-impedance SDA line. These two resets should have an overlap to have a proper initialization. It is also possible to reset the internal I2C-bus registers separately, and these registers will be set to their default values. 11.4 Defined I2C-bus address The I2C-bus address is defined for location: 001110P; the least significant bit is a programmable bit with the external pin A0_pin. Two possible options are available with this pin: • If A0 = 0 the following addresses are available: – Write: 00111000 = 38h – Read: 00111001 = 39h. • If A0 = 1 the following addresses are available: – Write: 00111010 = 3Ah – Read: 00111011 = 3Bh. 11.5 I2C-bus memory map specification The I2C-bus memory map contains all defined I2C-bus bits related to RDS, SRC and EPICS control and allocates EPICS, SRC and IFP RAM sizes. The memory spaces belonging to the AUDIO_EPICS are referred to as EPICS registers, and memory spaces belonging to the SRC/RDS EPICS are referred to as SRC registers. The RDS registers control the RDS1 and RDS2 blocks simultaneously while providing each RDS1 and RDS2 block with its own decoded data and status registers: the memory map is given in Table 21. Detailed memory map locations of the hardware registers related to the I2C-bus EPICS control are given in Table 23 and the I2C-bus RDS control are given in Table 24. Table 21 I2C-bus memory map; notes 1 and 2 BLOCK START (HEX) END (HEX) NAME NUMBER OF WORDS × BIT WIDTH (DEBUG PART) ACCESS − E000 FFFF not used −− SRC B880 DFFF reserved −− SRC B800 B87F SRC_YRAM 128 × 12 R/W SRC B000 B7FF reserved −− SRC AFFF AFFF IIC_SRC_PC 1 × 24 R/W SRC AFFE AFFE IIC_SRC_STAT 1 × 24 R/W SRC A300 AFFD reserved −− SRC A000 A2FF SRC_XRAM 768 × 24 R/W − 9000 9FFF reserved −− − 6030 8FFF not used −− Global 602F 602F IIC_DSP_CTR 1 × 24 R/W − 6010 602E not used −− RDS 6000 600F RDS 1 and 2 registers 12 × 16 see Table 24 EPICS 5FFF 5FFF IIC_SILICON_ID 1 × 32 read EPICS 4000 5FFE reserved −− − 3000 3FFF not used −− IFP 2C64 2FFF IFP registers all 16-bit width R/W |
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