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LM5160A Datasheet(PDF) 19 Page - Texas Instruments |
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LM5160A Datasheet(HTML) 19 Page - Texas Instruments |
19 / 28 page UV2 IN, UVLO(rising) UVLO(TH) UV1 R V V 1 R § · ¨ ¸ © ¹ IN(HYS) UVLO(HYS) UV2 V I R u SS Startup SS SS I T C V u O, max IN IN, ripple SW I D (1 D) C V F u u ' u 19 LM5160A, LM5160 www.ti.com SNVSA03C – OCTOBER 2014 – REVISED AUGUST 2016 Product Folder Links: LM5160A LM5160 Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated 8.2.1.2.6 VCC and Bootstrap Capacitor The VCC capacitor charges the bootstrap capacitor during the OFF-time of the high-side switch and powers internal logic circuits and the low-side sync FET gate driver. The bootstrap capacitor biases the high-side gate driver during the high-side FET ON-time. A good value for C5 ©VCC) is 1 µF. A good choice for C4 ©BST) is 10 nF. Both must be high-quality X7R ceramic capacitors. 8.2.1.2.7 Input Capacitor Selection The input capacitor must be large enough to limit the input voltage ripple to an acceptable level. Equation 15 provides the input capacitance CIN required for a worst-case input ripple of ∆VIN, ripple. (15) CIN (C1, C10) supplies most of the switch current during the ON-time to limit the voltage ripple at the VIN pin. At maximum load current, when the buck switch turns on, the current into the VIN pin quickly increases to the valley current of the inductor ripple and then ramps up to the peak of the inductor ripple during the ON-time of the high- side FET. The average current during the ON-time is the output load current. For a worst-case calculation, CIN must supply this average load current during the maximum ON-time, without letting the voltage at VIN drop more than the desired input ripple. For this design, the input voltage drop is limited to 0.5 V and the value of CIN is calculated using Equation 15. Based on Equation 15, the value of the input capacitor is calculated to be approximately 2.5 µF at D = 0.5. Taking into account the decrease in capacitance over an applied voltage, two standard value ceramic capacitors of 2.2 µF are selected for C1 and C10. The input capacitors must be rated for the maximum input voltage under all operating and transient conditions. A 100-V, X7R dielectric was selected for this design. A third input capacitor C2 may be needed in this design as a bypass path for the high frequency component of the input switching current. The value of C2 is 0.47 µF and this bypass capacitor must be placed directly across VIN and PGND (pin 3 and 2) near the IC. The CIN values and location are critical to reducing switching noise and transients. 8.2.1.2.8 Soft-Start Capacitor Selection The capacitor at the SS pin determines the soft-start time, that is, the time for the output voltage to reach its final steady-state value. The capacitor value is determined from Equation 16: (16) With C3 ©SS) set at 22 nF and the Vss = 2 V, ISS = 10 µA, the TStartup must measure approximately 4 ms. 8.2.1.2.9 EN/UVLO Resistor Selection The UVLO resistors R1 ®UV2) and R2 ®UV1) set the input undervoltage lockout threshold and hysteresis according to Equation 17 and Equation 18: (17) (18) From the Electrical Characteristics table, IUVLO(HYS) = 20 µA (typical). To design for VIN rising threshold (VIN, UVLO(rising)) at 10 V and EN/UVLO hysteresis of 2.5 V, Equation 17 and Equation 18 yield RUV1 = 17.98 kΩ and RUV2 = 125 kΩ. Selecting 1% standard value of R2 ®UV1) = 18.2 kΩ and R1 ®UV2) = 127 kΩ results in UVLO thresholds and hysteresis of 9.89 V and 2.54 V respectively. |
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