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SPX1587 Datasheet(PDF) 6 Page - Exar Corporation |
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SPX1587 Datasheet(HTML) 6 Page - Exar Corporation |
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6 / 11 page  S SP PX X1 15 58 87 7 3 3A A L Lo ow w D Drro op po ou utt V Vo olltta ag ge e R Re eg gu ulla atto orr © 2010 Exar Corporation 6/11 Rev. 2.0.0 thermal resistance of the SPX1587. The actual thermal resistance can be determined with experimentation. The SPX1587 power dissipation is calculated as follows: Maximum Junction Temperature range: Where θJA is the junction-to-ambient thermal resistance of the package. Maximum junction temperature must not exceed 125°C. RIPPLE REJECTION Ripple rejection can be improved by adding a capacitor between the ADJ pin and ground as shown in Figure 11. When ADJ pin bypassing is used, the value of the output capacitor required increases to its maximum. If the ADJ pin is not bypassed, the value of the output capacitor can be lowered to 22μF for an electrolytic aluminum capacitor or 10μF for a solid tantalum capacitor (Fig 10). However the value of the ADJ-bypass capacitor should be chosen with respect to the following equation: 1 6.28 Where C = value of the capacitor in Farads (select an equal or larger standard value) FR= ripple frequency in Hz R1= value of resistor R1 in Ohms. If an ADJ-bypass capacitor is used, the amplitude of the output ripple will be independent of the output voltage. If an ADJ- bypass capacitor is not used, the output ripple will be proportional to the ratio of the output voltage to the reference voltage: Where M = multiplier for the ripple seen when the ADJ pin is optimally bypassed. VREF=1.25V Ripple rejection for the adjustable version is showing in Figure 8. OUTPUT VOLTAGE The output of the adjustable regulator can be set to any voltage between 1.25V and 15V. The value of VOUT can be quickly approximated using the formula 1.25 Small correction to this formula is required de- pending on the values of resistors R1 and R2, since the adjustable pin current (approx 50μA) flows through R2. When IADJ is taken into account, the formula becomes 1 Where VREF=1.25V LAYOUT CONSIDERATIONS Parasitic line resistance can degrade load regulation. In order to avoid this, connect R1 directly to VOUT as illustrated in Figure 13. For the same reason, R2 should be connected to the negative side of the load. |
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