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SP6132HEU Datasheet(PDF) 4 Page - Exar Corporation |
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SP6132HEU Datasheet(HTML) 4 Page - Exar Corporation |
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4 / 14 page  4 Date:2/14/06 SP6132H High Voltage, Synchronous PWM Controller © Copyright 2006 Sipex Corporation General Overview The SP6132H is a fixed frequency, voltage mode, synchronous PWM controller optimized for high efficiency. The part has been designed to be especially attractive for split plane applica- tions which utilize 5V to power the controller and 3V to 12V for step down conversion. The heart of the SP6132H is a wide bandwidth transconductance amplifier designed to accom- modate Type II and Type III compensation schemes. A precision 0.8V reference present on the positive terminal of the error amplifier per- mits the programming of the output voltage down to 0.8V via the VFB pin. The output of the error amplifier, COMP, compared to a 1.1V peak-to-peak ramp is responsible for trailing edge PWM control. This voltage ramp and PWM control logic are governed by the internal oscil- lator that accurately sets the PWM frequency to 300kHz. FUNCTIONAL DIAGRAM THEORY OF OPERATION The SP6132H contains two unique control fea- tures that are very powerful in distributed appli- cations. First, asynchronous driver control is enabled during start up to prohibit the low side NFET from pulling down the output until the high side NFET has attempted to turn on. Sec- ond, a 100% duty cycle timeout ensures that the low side NFET is periodically enhanced during extended periods at 100% duty cycle. This guar- antees the synchronized refreshing of the BST capacitor during very large duty ratios. The SP6132H also contains a number of valu- able protection features. A programmable input (VIN) UVLO allows a user to set the exact value at which the conversion voltage is at a safe point to begin down conversion, and an internal VCC UVLO ensures that the controller itself has enough voltage to properly operate. Other pro- 1.7 V 1.7 V COMPARATOR ASYNC. STARTUP 0.4 V FAULT CLR COUNT 20 CLOCK PULSES 300 kHZ CLK CLOCK PULSE GENERATOR SS GL HOLD OFF 100% Protection Logic Q R S RESET DOMINANT QPWM CLK SYNCHRONOUS DRIVER GND 3 2 GL PWM LOOP 5 COMP POS REF FAULT 1 7 0.8V CORE REFERENCE V CC FAULT SOFTSTART INPUT RAMP = 1.1V VFBINT VPOS Gm Gm ERROR AMPLIFIER 9 GH 8 SWN 10 BST VFB SS 10 µA VCC VCC VCC FAULT REF OK FAULT POWER FAULT HICCUP FAULT REF OK VIN UVLO VCC UVLO 2.50 VON 2.20 V OFF 6 UVIN 4.25 V ON 4.05 V OFF Q VCC REF OK 200ms Delay COUNTER CLR CLK R SET DOMINANT S + - THERMAL SHUTDOWN 145 ˚C ON 135 ˚C OFF SHORT CIRCUIT DETECTION VFBINT + - VPOS 0.25 V THERMAL AND SHORT CIRCUIT PROTECTION UVLO COMPARATORS + - + - |
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