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LM5064 Datasheet(PDF) 41 Page - Texas Instruments |
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LM5064 Datasheet(HTML) 41 Page - Texas Instruments |
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41 / 62 page  LM5064 www.ti.com SNVS718E – JUNE 2011 – REVISED FEBRUARY 2013 MFR_SPECIFIC_04: MFR_PIN_OP_WARN_LIMIT (D4h) The MFR_PIN_OP_WARN_LIMIT PMBus command sets the input over-power warning threshold. In the event that the input power rises above the value set in this register, the PIN over-power flags are set in the respective registers and the SMBA is asserted. To access the MFR_PIN_OP_WARN_LIMIT register, use the PMBus Read/Write Word protocol. Reading/writing to this register should use the coefficients shown in Table 41. Table 26. MFR_PIN_OPWARN_LIMIT Register Value Meaning Default 0h – 0FFEh Value for input over-power warn limit 0FFFh 0FFFh Input over-power warning disabled n/a MFR_SPECIFIC_05: READ_PIN_PEAK (D5h) The READ_PIN_PEAK command will report the maximum input power measured since a Power On reset or the last CLEAR_PIN_PEAK command. To access the READ_PIN_PEAK command, use the PMBus Read Word protocol. Use the coefficients shown in Table 41. Table 27. READ_PIN_PEAK Register Value Meaning Default 0h – 0FFEh Maximum Value for input current x input 0h voltage since reset or last clear MFR_SPECIFIC_06: CLEAR_PIN_PEAK (D6h) The CLEAR_PIN_PEAK command will clear the PIN PEAK register. This command uses the PMBus Send Byte protocol. MFR_SPECIFIC_07: GATE_MASK (D7h) The GATE_MASK register allows the hardware to prevent fault conditions from switching off the MOSFET. When the bit is high, the corresponding FAULT has no control over the MOSFET gate. All status registers will still be updated (STATUS, DIAGNOSTIC) and an SMBA will still be asserted. This register is accessed with the PMBus Read / Write Byte protocol. The IIN/PFET Fault refers to the input current fault and the MOSFET power dissipation fault. There is no input power fault detection; only input power warning detection. WARNING Inhibiting the MOSFET switch off in response to over-current or circuit breaker fault conditions will likely result in the destruction of the MOSFET! This functionality should be used with great care and supervision! Table 28. MFR_SPECIFIC_07 GATE MASK Definitions Bit NAME Default 7 Not used, always 0 0 6 Not used, always 0 0 5 VIN UV FAULT 0 4 VIN OV FAULT 0 3 IIN/PFET FAULT 0 2 OVERTEMP FAULT 0 1 Not used, always 0 0 0 CIRCUIT BREAKER FAULT 0 Copyright © 2011–2013, Texas Instruments Incorporated Submit Documentation Feedback 41 Product Folder Links: LM5064 |
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