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LM4947 Datasheet(PDF) 9 Page - Texas Instruments

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Part No. LM4947
Description  Mono Class D and Stereo Audio Sub-System
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Maker  TI1 [Texas Instruments]
Homepage  http://www.ti.com
Logo TI1 - Texas Instruments

LM4947 Datasheet(HTML) 9 Page - Texas Instruments

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LM4947, LM4947TLEVAL
www.ti.com
SNAS349D – JUNE 2006 – REVISED MAY 2013
I
2C(1)(2)
The following specifications apply for VDD = 5V and 3.3V, TA = 25°C unless otherwise specified.
Symbol
Parameter
Conditions
LM4947
Units
(Limits)
Typical(3)
Limits(4)
t1
Clock Period
2.5
µs (max)
t2
Clock Setup Time
100
ns (min)
t3
Data Hold Time
100
ns (min)
t4
Start Condition Time
100
ns (min)
t5
Stop Condition Time
100
ns (min)
0.7xI2C
VIH
SPI Input Voltage High
V (min)
VDD
0.3xI2C
VIL
SPI Input Voltage Low
V (max)
VDD
(1)
Operating Ratings indicate conditions for which the device is functional, but do not ensure specific performance limits. For ensured
specifications and test conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed.
Some performance characteristics may degrade when the device is not operated under the listed test conditions.
(2)
All voltages are measured with respect to the ground pin, unless otherwise specified.
(3)
Typical specifications are specified at +25°C and represent the most likely parametric norm.
(4)
Tested limits are specified to AOQL (Average Outgoing Quality Level).
I
2C Protocol Information
The I2C address for the LM4947 is determined using the ID_ENB pin. The LM4947's two possible I2C chip
addresses are of the form 111110X10 (binary), where X1 = 0, if ID_ADDR is logic LOW; and X1 = 1, if ID_ENB is
logic HIGH. If the I2C interface is used to address a number of chips in a system, the LM4947's chip address can
be changed to avoid any possible address conflicts.
Figure 4. I2C Bus Format
Figure 5. I2C Timing Diagram
Copyright © 2006–2013, Texas Instruments Incorporated
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Product Folder Links: LM4947 LM4947TLEVAL


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