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LM4947 Datasheet(PDF) 24 Page - Texas Instruments

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Part No. LM4947
Description  Mono Class D and Stereo Audio Sub-System
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Maker  TI1 [Texas Instruments]
Homepage  http://www.ti.com
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LM4947 Datasheet(HTML) 24 Page - Texas Instruments

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LM4947, LM4947TLEVAL
SNAS349D – JUNE 2006 – REVISED MAY 2013
www.ti.com
APPLICATION INFORMATION
I
2C PIN DESCRIPTION
SDA: This is the serial data input pin.
SCL: This is the clock input pin.
ID_ENB: This is the address select input pin.
I
2C COMPATIBLE INTERFACE
The LM4947 uses a serial bus which conforms to the I2C protocol to control the chip's functions with two wires:
clock (SCL) and data (SDA). The clock line is uni-directional. The data line is bi-directional (open-collector). The
maximum clock frequency specified by the I2C standard is 400kHz. In this discussion, the master is the
controlling microcontroller and the slave is the LM4947.
The I2C address for the LM4947 is determined using the ID_ENB pin. The LM4947's two possible I2C chip
addresses are of the form 111110X10 (binary), where X1 = 0, if ID_ADDR is logic LOW; and X1 = 1, if ID_ENB is
logic HIGH. If the I2C interface is used to address a number of chips in a system, the LM4947's chip address can
be changed to avoid any possible address conflicts.
The bus format for the I2C interface is shown in Figure 4. The bus format diagram is broken up into six major
sections:
1. The "start" signal is generated by lowering the data signal while the clock signal is HIGH. The start signal will
alert all devices attached to the I2C bus to check the incoming address against their own address.
2. The 8-bit chip address is sent next, most significant bit first. The data is latched in on the rising edge of the
clock. Each address bit must be stable while the clock level is HIGH.
3. After the last bit of the address bit is sent, the master releases the data line HIGH (through a pull-up
resistor). Then the master sends an acknowledge clock pulse. If the LM4947 has received the address
correctly, then it holds the data line LOW during the clock pulse. If the data line is not held LOW during the
acknowledge clock pulse, then the master should abort the rest of the data transfer to the LM4947.
4. The 8 bits of data are sent next, most significant bit first. Each data bit should be valid while the clock level is
stable HIGH.
5. After the data byte is sent, the master must check for another acknowledge to see if the LM4947 received
the data.
6. The "stop" signal ends the transfer. To signal "stop", the data signal goes HIGH while the clock signal is
HIGH. The data line should be held HIGH when not in use.
I
2C INTERFACE POWER SUPPLY PIN (I2CV
DD)
The LM4947's I2C interface is powered up through the I2CVDD pin. The LM4947's I
2C interface operates at a
voltage level set by the I2CVDD pin which can be set independent to that of the main power supply pin VDD. This
is ideal whenever logic levels for the I2C interface are dictated by a microcontroller or microprocessor that is
operating at a lower supply voltage than the main battery of a portable system.
Table 1. Chip Address
A7
A6
A5
A4
A3
A2
A1
A0
Chip Address
1
1
1
1
1
0
EC
0
ID_ADDR = 0
1
1
1
1
1
0
0
0
ID_ADDR = 1
1
1
1
1
1
0
1
0
24
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Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: LM4947 LM4947TLEVAL


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