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CY7C1069AV33
Document #: 38-05255 Rev. *D
Page 6 of 9
Switching Waveforms (continued)
Write Cycle No. 1 (CE1 Controlled)
tHD
tSD
tSCE
tSA
tHA
tAW
tPWE
tWC
BW
DATAI/O
ADDRESS
CE
WE
[13, 14, 15]
t
Write Cycle No. 2 (WE Controlled, OE LOW)
tHD
tSD
tSCE
tHA
tAW
tPWE
tWC
DATA I/O
ADDRESS
CE
WE
tSA
tLZWE
tHZWE
[13, 14, 15]
Truth Table
CE1
CE2
OE
WE
I/O0–I/O7
Mode
Power
H
X
X
X
High-Z
Power-down
Standby (ISB)
X
L
X
X
High-Z
Power-down
Standby (ISB)
L
H
L
H
Data Out
Read All Bits
Active (ICC)
L
H
X
L
Data In
Write All Bits
Active (ICC)
L
H
H
H
High-Z
Selected, Outputs Disabled
Active (ICC)
Notes:
12. Address valid prior to or coincident with CE1 transition LOW and CE2 transition HIGH.
13. Data I/O is high-impedance if OE = VIH.
14. If CE1 goes HIGH / CE2 LOW simultaneously with WE going HIGH, the output remains in a high–impedance state.
15. CE above is defined as a combination of CE1 and CE2. It is active low.
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