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PCI7621GHK Datasheet(PDF) 1 Page - Texas Instruments |
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PCI7621GHK Datasheet(HTML) 1 Page - Texas Instruments |
1 / 7 page www.ti.com FEATURES PCI7621/PCI7611 PCI7421/PCI7411 SLLA248 – JULY 2006 Dual/Single Socket CardBus and UltraMedia Controller With Integrated 1394a-2000 OHCI Two-Port PHY/Link-Layer Controller With Dedicated Flash Media Socket • Fully interoperable with FireWire™ and i.LINK™ implementations of IEEE Std 1394 • PC Card Standard 8.1 compliant • Compliant with Intel Mobile Power Guideline • PCI Bus Power Management Interface 2000 Specification 1.1 compliant • Full IEEE Std 1394a-2000 support includes: • Advanced Configuration and Power Interface connection debounce, arbitrated short reset, (ACPI) Specification 2.0 compliant multispeed concatenation, arbitration • PCI Local Bus Specification Revision 2.3 acceleration, fly-by concatenation, and port compliant disable/suspend/resume • PC 98/99 and PC2001 compliant • Power-down features to conserve energy in • Windows Logo Program 2.0 compliant battery-powered applications include: • PCI Bus Interface Specification for automatic device power down during PCI-to-CardBus Bridges suspend, PCI power management for • Fully compliant with provisions of IEEE Std link-layer, and inactive ports powered down, 1394-1995 for a high-performance serial bus ultralow-power sleep mode and IEEE Std 1394a-2000 • Two IEEE Std 1394a-2000 fully compliant • Fully compliant with 1394 Open Host cable ports at 100M bits/s, 200M bits/s, and Controller Interface Specification 1.1 400M bits/s • 1.5-V core logic and 3.3-V I/O cells with • Cable ports monitor line conditions for active internal voltage regulator to generate 1.5-V connection to remote node core VCC • Cable power presence monitoring • Universal PCI interfaces compatible with • Separate cable bias (TPBIAS) for each port 3.3-V and 5-V PCI signaling environments • Physical write posting of up to three • Supports PC Card or CardBus with hot outstanding transactions insertion and removal • PCI burst transfers and deep FIFOs to • Supports 132-MBps burst transfers to tolerate large host latency maximize data throughput on both the PCI • External cycle timer control for customized bus and the CardBus synchronization • Supports serialized IRQ with PCI interrupts • Extended resume signaling for compatibility • Programmable multifunction terminals with legacy DV components • Many interrupt modes supported • PHY-Link logic performs system initialization • Serial ROM interface for loading subsystem and arbitration functions ID and subsystem vendor ID • PHY-Link encode and decode functions • ExCA-compatible registers are mapped in included for data-strobe bit level encoding memory or I/O space • PHY-Link incoming data resynchronized to • Intel 82365SL-DF register compatible local clock • Supports ring indicate, SUSPEND, and PCI • Low-cost 24.576-MHz crystal provides CLKRUN protocols transmit and receive data at 100M bits/s, 200M bits/s, and 400M bits/s • Provides VGA/palette memory and I/O, and subtractive decoding options, LED activity • Node power class information signaling for terminals system power management Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. FireWire is a trademark of Apple Computer, Inc.. i.LINK is a trademark of Sony Corporation of America. PRODUCTION DATA information is current as of publication date. Copyright © 2006, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
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