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DESCRIPTION

PCI7620/PCI7420

SLLA252 – JULY 2006

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Register access fail interrupt when the PHY

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PME support per 1394 Open Host Controller

SCLK is not active

Interface Specification

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PCI power-management D0, D1, D2, and D3

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Advanced submicron, low-power CMOS

power states

technology

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Initial bandwidth available and initial

channels available registers

The Texas Instruments PCI7620 device is an integrated dual-socket PC Card controller, Smart Card controller,

IEEE 1394 open HCI host controller, and PHY, Secure Digital (SD)/MultiMediaCard (MMC), Memory Stick

(MS)/MS-Pro controller. This high-performance integrated solution provides the latest in PC Card, Smart Card,

IEEE 1394, SD, MMC, and Memory Stick technology.

The Texas Instruments PCI7420 device is an integrated dual-socket PC Card controller, IEEE 1394 Open HCI

host controller, and PHY, SD/MMC MS/MS-Pro controller. This high-performance integrated solution provides

the latest in PC Card, IEEE 1394, SD, MMC, and Memory Stick technology.

For the remainder of this document, the PCI7x20 device refers to both devices: PCI7620 and PCI7420.

The PCI7620 and PCI7420 are four-function PCI devices compliant with PCI Local Bus Specification, Revision

2.3.

Functions 0 and 1 provide the independent PC Card socket controllers compliant with the PC Card Standard

(Release 8.0). The PCI7x20 device provides features that make it the best choice for bridging between the PCI

bus, PC Cards, and Smart Cards and supports any combination of 16-bit, CardBus PC Cards, or Smart Card

adapter in the socket powered at 5 V or 3.3 V, as required.

There are no PCMCIA card and socket service software changes required to move systems from the existing

CardBus socket controller to the PCI7x20 device. The PCI7x20 device is register compatible with the Intel

82365SL–DF ExCA controller and implements the host interface defined in the PC Card Standard. The PCI7x20

internal data path logic allows the host to access 8-, 16-, and 32-bit cards using full 32-bit PCI cycles for

maximum performance. Independent buffering and the pipeline architecture provides an unsurpassed

performance level with sustained bursting. The PCI7x20 device can be programmed to accept posted writes to

improve bus utilization. All card signals are internally buffered to allow hot insertion and removal without external

buffering.

Function 2 of the PCI7x20 device is an integrated IEEE 1394a–2000 open host controller interface (OHCI)

PHY/link-layer controller (LLC) device that is fully compliant with the PCI Local Bus Specification, the PCI Bus

Power Management Interface Specification, IEEE Std 1394–1995, IEEE Std 1394a–2000, and the 1394 Open

Host Controller Interface Specification. It is capable of transferring data between the 33-MHz PCI bus and the

1394 bus at 100M bits/s, 200M bits/s, and 400M bits/s. The PCI7x20 device provides two 1394 ports that have

separate cable bias (TPBIAS). The PCI7x20 device also supports the IEEE Std 1394a–2000 power-down

features for battery-operated applications and arbitration enhancements.

As required by the 1394 Open Host Controller Interface Specification and IEEE Std 1394a–2000, internal control

registers are memory-mapped and nonprefetchable. The PCI configuration header is accessed through

configuration cycles specified by PCI, and it provides plug-and-play (PnP) compatibility. Furthermore, the

PCI7x20 device is compliant with the PCI Bus Power Management Interface Specification. The PCI7x20 device

supports the D0, D1, D2, and D3 power states.

The PCI7x20 design provides PCI bus master bursting, and is capable of transferring a cacheline of data at

132M bytes/s after connection to the memory controller. Because PCI latency can be large, deep FIFOs are

provided to buffer the IEEE 1394 data.

The PCI7x20 device provides physical write posting buffers and a highly-tuned physical data path for SBP-2

performance. The PCI7x20 device also provides multiple isochronous contexts, multiple cacheline burst

transfers, advanced internal arbitration, and bus-holding buffers.

The PCI7x20 PHY-layer provides the digital and analog transceiver functions needed to implement a two-port

node in a cable-based 1394 network. Each cable port incorporates two differential line transceivers. The

transceivers include circuitry to monitor the line conditions as needed for determining connection status, for

initialization and arbitration, and for packet reception and transmission.

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