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PCI7610 Datasheet(PDF) 1 Page - Texas Instruments |
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PCI7610 Datasheet(HTML) 1 Page - Texas Instruments |
1 / 6 page www.ti.com FEATURES PCI7610 SLLA251 – JULY 2006 PC Card, UltraMedia™, and Integrated 1394a-2000 OHCI Two-Port PHY/Link-Layer Controller • Fully interoperable with FireWire™ and i.LINK™ implementations of IEEE Std 1394 • PC Card Standard 8.0 compliant • Compliant with Intel Mobile Power Guideline • PCI Bus Power Management Interface 2000 Specification 1.1 compliant • Full IEEE Std 1394a-2000 support includes: • Advanced Configuration and Power Interface connection debounce, arbitrated short reset, (ACPI) Specification 2.0 compliant multispeed concatenation, arbitration • PCI Local Bus Specification Revision 2.3 acceleration, fly-by concatenation, and port compliant disable/suspend/resume • PC 98/99 and PC2001 compliant • Power-down features to conserve energy in • Compliant with the PCI Bus Interface battery-powered applications include: Specification for PCI-to-CardBus Bridges automatic device power down during • Fully compliant with provisions of IEEE Std suspend, PCI power management for 1394-1995 for a high-performance serial bus link-layer, and inactive ports powered down, and IEEE Std 1394a-2000 ultralow-power sleep mode • Fully compliant with 1394 Open Host • Two IEEE Std 1394a-2000 fully compliant Controller Interface Specification 1.1 cable ports at 100M bits/s, 200M bits/s, and • 1.8-V core logic and 3.3-V I/O cells with 400M bits/s internal voltage regulator to generate 1.8-V • Cable ports monitor line conditions for active core VCC connection to remote node • Universal PCI interfaces compatible with • Cable power presence monitoring 3.3-V and 5-V PCI signaling environments • Separate cable bias (TPBIAS) for each port • Supports PC Card or CardBus with hot • Physical write posting of up to three insertion and removal outstanding transactions • Supports 132-MBps burst transfers to • PCI burst transfers and deep FIFOs to maximize data throughput on both the PCI tolerate large host latency bus and the CardBus • External cycle timer control for customized • Supports serialized IRQ with PCI interrupts synchronization • Programmable multifunction terminals • Extended resume signaling for compatibility • Many interrupt modes supported with legacy DV components • Serial ROM interface for loading subsystem • PHY-Link logic performs system initialization ID and subsystem vendor ID and arbitration functions • ExCA-compatible registers are mapped in • PHY-Link encode and decode functions memory or I/O space included for data-strobe bit level encoding • Intel 82365SL–DF register compatible • PHY-Link incoming data resynchronized to • Supports ring indicate, SUSPEND, and PCI local clock CCLKRUN protocol and PCI bus Lock (LOCK) • Low-cost 24.576-MHz crystal provides • Provides VGA/palette memory and I/O, and transmit and receive data at 100M bits/s, subtractive decoding options, LED activity 200M bits/s, and 400M bits/s terminals Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. UltraMedia is a trademark of Texas Instruments.. FireWire is a trademark of Apple Computer, Inc.. i.LINK is a trademark of Sony Corporation of America. PRODUCTION DATA information is current as of publication date. Copyright © 2006, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
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