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PCI2050BIGHK Datasheet(PDF) 8 Page - Texas Instruments |
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PCI2050BIGHK Datasheet(HTML) 8 Page - Texas Instruments |
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8 / 88 page  1−1 1 Introduction The Texas Instruments PCI2050B PCI-to-PCI bridge provides a high performance connection path between two peripheral component interconnect (PCI) buses operating at a maximum bus frequency of 66-MHz. Transactions occur between masters on one and targets on another PCI bus, and the PCI2050B bridge allows bridged transactions to occur concurrently on both buses. The bridge supports burst mode transfers to maximize data throughput, and the two bus traffic paths through the bridge act independently. The PCI2050B bridge is compliant with the PCI Local Bus Specification, and can be used to overcome the electrical loading limits of 10 devices per PCI bus and one PCI device per extension slot by creating hierarchical buses. The PCI2050B provides two-tier internal arbitration for up to nine secondary bus masters and may be implemented with an external bus arbiter. The CompactPCI™ hot-swap extended PCI capability makes the PCI2050B bridge an ideal solution for multifunction compact PCI cards and adapting single function cards to hot-swap compliance. The PCI2050B bridge is compliant with the PCI-to-PCI Bridge Specification (Revision 1.1). The PCI2050B bridge provides compliance for PCI Bus Power Management Interface Specification (Revision 1.1). The PCI2050B bridge has been designed to lead the industry in power conservation and data throughput. An advanced CMOS process achieves low system power consumption while operating at PCI clock rates up to 66-MHz. 1.1 Features The PCI2050B bridge supports the following features: • Two 32-bit, 66-MHz PCI buses • 3.3-V core logic with universal PCI interfaces compatible with 3.3-V and 5-V PCI signaling environments • Internal two-tier arbitration for up to nine secondary bus masters and supports an external secondary bus arbiter • Ten secondary PCI clock outputs • Independent read and write buffers for each direction • Burst data transfers with pipeline architecture to maximize data throughput in both directions • Supports write combing for enhanced data throughput • Up to three delayed transactions in both directions • Supports the frame-to-frame delay of only four PCI clocks from one bus to another • Bus locking propagation • Predictable latency per PCI Local Bus Specification • Architecture configurable for PCI Bus Power Management Interface Specification • CompactPCI hot-swap functionality • Secondary bus is driven low during reset • VGA/palette memory and I/O decoding options • Advanced submicron, low-power CMOS technology • 208-terminal PDV, 208-terminal PPM, or 257-terminal MicroStar BGA™ package |
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