Data Output

by Transmitter

SCL From

Master

Start

Condition

S

1

2

8

9

Data Output

by Receiver

Clock Pulse for ACK

NACK

ACK

SDA

SCL

Master

Transmitter/

Receiver

Slave

Receiver

Slave

Transmitter/

Receiver

Master

Transmitter

Master

Transmitter/

Receiver

Multiplexer

Slave

PCA9544A

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SCPS146E – OCTOBER 2005 – REVISED JUNE 2014

Programming (continued)

A device generating a message is a transmitter; a device receiving a message is the receiver. The device that

controls the message is the master, and the devices that are controlled by the master are the slaves (see

Figure 5).

Figure 5. System Configuration

The number of data bytes transferred between the start and the stop conditions from transmitter to receiver is not

limited. Each byte of eight bits is followed by one ACK bit. The transmitter must release the SDA line before the

receiver can send an ACK bit.

When a slave receiver is addressed, it must generate an acknowledge (ACK) after the reception of each byte.

Also, a master must generate an ACK after the reception of each byte that has been clocked out of the slave

transmitter. The device that acknowledges must pull down the SDA line during the ACK clock pulse so that the

SDA line is stable low during the high pulse of the ACK-related clock period (see Figure 6). Setup and hold times

must be taken into account.

A master receiver must signal an end of data to the transmitter by not generating an acknowledge (NACK) after

the last byte has been clocked out of the slave. This is done by the master receiver by holding the SDA line high.

In this event, the transmitter must release the data line to enable the master to generate a stop condition.

Data is transmitted to the PCA9544A control register using the write mode shown in Figure 7.

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