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PCA9535DW Datasheet(PDF) 1 Page - Texas Instruments |
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PCA9535DW Datasheet(HTML) 1 Page - Texas Instruments |
1 / 42 page DB, DBQ, DGV, DW, OR PW PACKAGE (TOP VIEW) INT A1 A2 P00 P01 P02 P03 P04 P05 P06 P07 GND VCC SDA SCL A0 P17 P16 P15 P14 P13 P12 P11 P10 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 7 8 9 10 11 1 2 3 4 5 6 18 17 16 15 14 13 RGE PACKAGE (TOP VIEW) 19 12 P00 P01 P02 P03 P04 P05 A0 P17 P16 P15 P14 P13 A0 P17 P16 P15 P14 P13 24 22 21 20 19 23 7 9 10 11 12 8 P00 P01 P02 P03 P04 P05 1 2 3 4 5 6 18 17 16 15 14 13 RTW PACKAGE (TOP VIEW) Product Folder Sample & Buy Technical Documents Tools & Software Support & Community PCA9535 SCPS129J – AUGUST 2005 – REVISED JUNE 2014 PCA9535 Remote 16-BIT I2C and SMBus Low-Power I/O Expander With Interrupt Output and Configuration Registers 1 Features 2 Description This 16-bit I/O expander for the two-line bidirectional 1 • Low Standby-Current Consumption of 1 μA Max bus (I2C) is designed for 2.3-V to 5.5-V VCC • I2C to Parallel Port Expander operation. It provides general-purpose remote I/O • Open-Drain Active-Low Interrupt Output expansion for most microcontroller families via the I2C interface [serial clock (SCL), serial data (SDA)]. • 5-V Tolerant I/O Ports • Compatible With Most Microcontrollers The PCA9535 consists of two 8-bit Configuration (input or output selection), Input Port, Output Port, • 400-kHz Fast I2C Bus and Polarity Inversion (active-high or active-low • Address by Three Hardware Address Pins for Use operation) registers. At power on, the I/Os are of up to Eight Devices configured as inputs. The system master can enable • Polarity Inversion Register the I/Os as either inputs or outputs by writing to the I/O configuration bits. The data for each input or • Latched Outputs With High-Current Drive output is kept in the corresponding Input or Output Capability for Directly Driving LEDs Port register. The polarity of the Input Port register • Latch-Up Performance Exceeds 100 mA Per can be inverted with the Polarity Inversion register. All JESD 78, Class II registers can be read by the system master. • ESD Protection Exceeds JESD 22 The system master can reset the PCA9535 in the – 2000-V Human-Body Model (A114-A) event of a timeout or other improper operation by – 1000-V Charged-Device Model (C101) utilizing the power-on reset feature, which puts the registers in their default state and initializes the I2C/SMBus state machine. The PCA9535 open-drain interrupt (INT) output is activated when any input state differs from its corresponding Input Port register state and is used to indicate to the system master that an input state has changed. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) SSOP (16) 6.20 mm × 5.30 mm PCA9535 VQFN (16) 4.00 mm × 4.00 mm QFN (16) 3.00 mm × 3.00 mm (1) For all available packages, see the orderable addendum at the end of the datasheet. 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. |
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