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PCA9515ADGKTG4 Datasheet(PDF) 1 Page - Texas Instruments |
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PCA9515ADGKTG4 Datasheet(HTML) 1 Page - Texas Instruments |
1 / 24 page D, DCT, DGK, OR PW PACKAGE (TOP VIEW) 1 2 3 4 V CC SCL1 SDA1 EN NC SCL0 SDA0 GND 8 7 6 5 NC No internal connection – DRG PACKAGE (TOP VIEW) 1 2 3 4 V CC SCL1 SDA1 EN NC SCL0 SDA0 GND 8 7 6 5 Product Folder Sample & Buy Technical Documents Tools & Software Support & Community PCA9515A SCPS150D – DECEMBER 2005 – REVISED JUNE 2014 Dual Bidirectional I2C Bus and SMBus Repeater The I2C bus capacitance limit of 400 pF restricts the 1 Features number of devices and bus length. Using the 1 • Two-Channel Bidirectional Buffers PCA9515A enables the system designer to isolate • I2C Bus and SMBus Compatible two halves of a bus, accommodating more I2C devices or longer trace lengths. • Active-High Repeater-Enable Input • Open-Drain I2C I/O The PCA9515A has an active-high enable (EN) input with an internal pullup, which allows the user to select • 5.5-V Tolerant I2C I/O and Enable Input Support when the repeater is active. This can be used to Mixed-Mode Signal Operation isolate a badly behaved slave on power-up reset. It • Lockup-Free Operation never should change state during an I2C operation, • Accommodates Standard Mode and Fast Mode because disabling during a bus operation hangs the I2C Devices and Multiple Masters bus, and enabling part way through a bus cycle could confuse the I2C parts being enabled. The EN input • Powered-Off High-Impedance I2C Pins should change state only when the global bus and • Latch-Up Performance Exceeds 100 mA Per the repeater port are in an idle state, to prevent JESD 78, Class II system failures. • ESD Protection Exceeds JESD 22 The PCA9515A also can be used to run two buses: – 2000-V Human-Body Model (A114-A) one at 5-V interface levels and the other at 3.3-V – 200-V Machine Model (A115-A) interface levels, or one at 400-kHz operating frequency and the other at 100-kHz operating – 1000-V Charged-Device Model (C101) frequency. If the two buses are operating at different frequencies, the 100-kHz bus must be isolated when 2 Description the 400-kHz operation of the other bus is required. If This dual bidirectional I2C buffer is operational at 2.3- the master is running at 400 kHz, the maximum V to 3.6-V VCC. system operating frequency may be less than 400 kHz, because of the delays that are added by the The PCA9515A is a BiCMOS integrated circuit repeater. intended for I2C bus and SMBus systems applications. The device contains two identical The PCA9515A does not support clock stretching bidirectional open-drain buffer circuits that enable I2C across the repeater. and similar bus systems to be extended without degradation of system performance. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) The PCA9515A buffers both the serial data (SDA) and serial clock (SCL) signals on the I2C bus, while SOIC (8) 4.90 mm × 3.91 mm PCA9515A retaining all the operating modes and features of the SON (8) 3.00 mm × 3.00 mm I2C system. This enables two buses of 400-pF bus (1) For all available packages, see the orderable addendum at capacitance to be connected in an I2C application. the end of the datasheet. 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. |
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