SDAA

SDAB

SCL

Rise time accelerator pulling SDAB high

after SDAA overshoots past 500mV

Not Recommended for New Designs

PCA9517

SCPS157E – DECEMBER 2007 – REVISED JUNE 2014

www.ti.com

8.2 Feature Description

8.2.1 Clock Stretching Errata

Description

Due to the static offset on the B-side and the possibility of an overshoot above 500mV during events like clock

stretching, the device should not be used with rise time accelerators on the B-side.

Figure 5. Waveform of Clock Stretching with Rise Time Accelerator on the Bus

System Impact

An incorrect logic state will be transferred to circuits, creating an I2C communication failure on the bus.

System Workaround

Usage of the TCA9517 is recommended.

There are two possible workarounds to avoid an I2C communication failure:

•

Removing rise-time accelerators from the B-side bus

•

Adding a larger capacitive load to the bus will limit the overshoot

8.2.2 Load Dependent Undershoot Errata

Description

There is a case in which a combination of weak pull-up resistance and light bus loading will cause

communication failure through the bus due to undershoot. During a low-to-high transition, when the B-side

as a valid low coming from the B-side, causing the A-side to be pulled down by the buffer. The A-side being

improperly pulled down by the buffer will trigger the B-side to be pulled low. Since the B-side will be pulled to

500mV, this will not force the A-side to stay low. As the A-side begins transitioning high again, the issue will

repeat itself.

System Impact

An incorrect logic state will be transferred to circuits, creating an I2C communication failure on the bus.

System Workaround

Usage of the TCA9517 is recommended.

There are two possible workarounds to avoid an I2C communication failure:

•

Removing rise-time accelerators from the B-side bus

•

Adding a larger capacitive load to the bus will limit the overshoot

10

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